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arm64/vmm: Move nVHE-only code to the new file
There are some functions that are only needed in non-VHE mode. These are used to handle hypervisor calls from the kernel, and to manage the page tables in EL2. As these won't be used by the VHE code we can move them to the non-VHE specific files. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46073
This commit is contained in:
Andrew Turner
parent
3d61bcf1eb
commit
4b6c9f84de
4 changed files with 173 additions and 162 deletions
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@ -39,8 +39,6 @@
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struct hypctx;
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uint64_t vmm_hyp_enter(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t,
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uint64_t, uint64_t, uint64_t);
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uint64_t VMM_HYP_FUNC(do_call_guest)(struct hypctx *);
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static void
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@ -665,75 +663,3 @@ VMM_HYP_FUNC(s2_tlbi_all)(uint64_t vttbr)
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WRITE_SPECIALREG(vttbr_el2, host_vttbr);
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isb();
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}
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static int
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vmm_dc_civac(uint64_t start, uint64_t len)
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{
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size_t line_size, end;
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uint64_t ctr;
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ctr = READ_SPECIALREG(ctr_el0);
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line_size = sizeof(int) << CTR_DLINE_SIZE(ctr);
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end = start + len;
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dsb(ishst);
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/* Clean and Invalidate the D-cache */
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for (; start < end; start += line_size)
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__asm __volatile("dc civac, %0" :: "r" (start) : "memory");
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dsb(ish);
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return (0);
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}
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static int
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vmm_el2_tlbi(uint64_t type, uint64_t start, uint64_t len)
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{
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uint64_t end, r;
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dsb(ishst);
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switch (type) {
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default:
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case HYP_EL2_TLBI_ALL:
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__asm __volatile("tlbi alle2" ::: "memory");
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break;
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case HYP_EL2_TLBI_VA:
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end = TLBI_VA(start + len);
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start = TLBI_VA(start);
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for (r = start; r < end; r += TLBI_VA_L3_INCR) {
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__asm __volatile("tlbi vae2is, %0" :: "r"(r));
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}
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break;
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}
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dsb(ish);
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return (0);
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}
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uint64_t
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vmm_hyp_enter(uint64_t handle, uint64_t x1, uint64_t x2, uint64_t x3,
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uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7)
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{
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switch (handle) {
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case HYP_ENTER_GUEST:
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return (VMM_HYP_FUNC(enter_guest)((struct hyp *)x1,
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(struct hypctx *)x2));
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case HYP_READ_REGISTER:
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return (VMM_HYP_FUNC(read_reg)(x1));
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case HYP_CLEAN_S2_TLBI:
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VMM_HYP_FUNC(clean_s2_tlbi());
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return (0);
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case HYP_DC_CIVAC:
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return (vmm_dc_civac(x1, x2));
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case HYP_EL2_TLBI:
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return (vmm_el2_tlbi(x1, x2, x3));
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case HYP_S2_TLBI_RANGE:
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VMM_HYP_FUNC(s2_tlbi_range)(x1, x2, x3, x4);
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return (0);
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case HYP_S2_TLBI_ALL:
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VMM_HYP_FUNC(s2_tlbi_all)(x1);
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return (0);
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case HYP_CLEANUP: /* Handled in vmm_hyp_exception.S */
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default:
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break;
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}
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return (0);
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}
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@ -145,29 +145,6 @@
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b handle_\name
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.endm
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.section ".vmm_vectors","ax"
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.align 11
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hyp_init_vectors:
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vempty /* Synchronous EL2t */
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vempty /* IRQ EL2t */
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vempty /* FIQ EL2t */
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vempty /* Error EL2t */
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vempty /* Synchronous EL2h */
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vempty /* IRQ EL2h */
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vempty /* FIQ EL2h */
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vempty /* Error EL2h */
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vector hyp_init /* Synchronous 64-bit EL1 */
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vempty /* IRQ 64-bit EL1 */
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vempty /* FIQ 64-bit EL1 */
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vempty /* Error 64-bit EL1 */
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vempty /* Synchronous 32-bit EL1 */
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vempty /* IRQ 32-bit EL1 */
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vempty /* FIQ 32-bit EL1 */
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vempty /* Error 32-bit EL1 */
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.text
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.align 11
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hyp_vectors:
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@ -191,50 +168,6 @@ hyp_vectors:
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vempty /* FIQ 32-bit EL1 */
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vempty /* Error 32-bit EL1 */
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/*
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* Initialize the hypervisor mode with a new exception vector table, translation
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* table and stack.
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*
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* Expecting:
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* x0 - translation tables physical address
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* x1 - stack top virtual address
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* x2 - TCR_EL2 value
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* x3 - SCTLR_EL2 value
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* x4 - VTCR_EL2 value
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*/
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LENTRY(handle_hyp_init)
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/* Install the new exception vectors */
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adrp x6, hyp_vectors
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add x6, x6, :lo12:hyp_vectors
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msr vbar_el2, x6
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/* Set the stack top address */
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mov sp, x1
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/* Use the host VTTBR_EL2 to tell the host and the guests apart */
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mov x9, #VTTBR_HOST
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msr vttbr_el2, x9
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/* Load the base address for the translation tables */
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msr ttbr0_el2, x0
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/* Invalidate the TLB */
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dsb ish
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tlbi alle2
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dsb ishst
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isb
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/* Use the same memory attributes as EL1 */
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mrs x9, mair_el1
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msr mair_el2, x9
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/* Configure address translation */
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msr tcr_el2, x2
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isb
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/* Set the system control register for EL2 */
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msr sctlr_el2, x3
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/* Set the Stage 2 translation control register */
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msr vtcr_el2, x4
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/* Return success */
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mov x0, #0
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/* MMU is up and running */
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ERET
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LEND(handle_hyp_init)
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.macro do_world_switch_to_host
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save_guest_registers
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restore_host_registers
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@ -364,24 +297,3 @@ ENTRY(VMM_HYP_FUNC(do_call_guest))
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/* Enter guest */
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ERET
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END(VMM_HYP_FUNC(do_call_guest))
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/*
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* Usage:
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* void vmm_cleanup(uint64_t handle, void *hyp_stub_vectors)
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*
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* Expecting:
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* x1 - physical address of hyp_stub_vectors
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*/
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LENTRY(vmm_cleanup)
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/* Restore the stub vectors */
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msr vbar_el2, x1
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/* Disable the MMU */
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dsb sy
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mrs x2, sctlr_el2
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bic x2, x2, #SCTLR_EL2_M
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msr sctlr_el2, x2
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isb
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ERET
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LEND(vmm_cleanup)
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@ -1,8 +1,12 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Andrew Turner
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* Copyright (c) 2024 Arm Ltd
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*
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* This work was supported by Innovate UK project 105694, "Digital Security
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* by Design (DSbD) Technology Platform Prototype".
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -29,3 +33,82 @@
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#define VMM_HYP_FUNC(func) vmm_nvhe_ ## func
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#include "vmm_hyp.c"
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uint64_t vmm_hyp_enter(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t,
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uint64_t, uint64_t, uint64_t);
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/*
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* Handlers for EL2 addres space. Only needed by non-VHE code as in VHE the
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* kernel is in EL2 so pmap will manage the address space.
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*/
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static int
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vmm_dc_civac(uint64_t start, uint64_t len)
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{
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size_t line_size, end;
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uint64_t ctr;
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ctr = READ_SPECIALREG(ctr_el0);
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line_size = sizeof(int) << CTR_DLINE_SIZE(ctr);
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end = start + len;
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dsb(ishst);
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/* Clean and Invalidate the D-cache */
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for (; start < end; start += line_size)
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__asm __volatile("dc civac, %0" :: "r" (start) : "memory");
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dsb(ish);
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return (0);
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}
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static int
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vmm_el2_tlbi(uint64_t type, uint64_t start, uint64_t len)
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{
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uint64_t end, r;
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dsb(ishst);
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switch (type) {
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default:
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case HYP_EL2_TLBI_ALL:
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__asm __volatile("tlbi alle2" ::: "memory");
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break;
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case HYP_EL2_TLBI_VA:
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end = TLBI_VA(start + len);
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start = TLBI_VA(start);
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for (r = start; r < end; r += TLBI_VA_L3_INCR) {
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__asm __volatile("tlbi vae2is, %0" :: "r"(r));
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}
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break;
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}
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dsb(ish);
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return (0);
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}
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uint64_t
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vmm_hyp_enter(uint64_t handle, uint64_t x1, uint64_t x2, uint64_t x3,
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uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7)
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{
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switch (handle) {
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case HYP_ENTER_GUEST:
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return (VMM_HYP_FUNC(enter_guest)((struct hyp *)x1,
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(struct hypctx *)x2));
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case HYP_READ_REGISTER:
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return (VMM_HYP_FUNC(read_reg)(x1));
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case HYP_CLEAN_S2_TLBI:
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VMM_HYP_FUNC(clean_s2_tlbi());
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return (0);
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case HYP_DC_CIVAC:
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return (vmm_dc_civac(x1, x2));
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case HYP_EL2_TLBI:
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return (vmm_el2_tlbi(x1, x2, x3));
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case HYP_S2_TLBI_RANGE:
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VMM_HYP_FUNC(s2_tlbi_range)(x1, x2, x3, x4);
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return (0);
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case HYP_S2_TLBI_ALL:
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VMM_HYP_FUNC(s2_tlbi_all)(x1);
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return (0);
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case HYP_CLEANUP: /* Handled in vmm_hyp_exception.S */
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default:
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break;
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}
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return (0);
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}
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@ -28,3 +28,93 @@
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#define VMM_HYP_FUNC(func) vmm_nvhe_ ## func
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#include "vmm_hyp_exception.S"
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.section ".vmm_vectors","ax"
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.align 11
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hyp_init_vectors:
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vempty /* Synchronous EL2t */
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vempty /* IRQ EL2t */
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vempty /* FIQ EL2t */
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vempty /* Error EL2t */
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vempty /* Synchronous EL2h */
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vempty /* IRQ EL2h */
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vempty /* FIQ EL2h */
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vempty /* Error EL2h */
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vector hyp_init /* Synchronous 64-bit EL1 */
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vempty /* IRQ 64-bit EL1 */
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vempty /* FIQ 64-bit EL1 */
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vempty /* Error 64-bit EL1 */
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vempty /* Synchronous 32-bit EL1 */
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vempty /* IRQ 32-bit EL1 */
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vempty /* FIQ 32-bit EL1 */
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vempty /* Error 32-bit EL1 */
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.text
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/*
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* Initialize the hypervisor mode with a new exception vector table, translation
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* table and stack.
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*
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* Expecting:
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* x0 - translation tables physical address
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* x1 - stack top virtual address
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* x2 - TCR_EL2 value
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* x3 - SCTLR_EL2 value
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* x4 - VTCR_EL2 value
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*/
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LENTRY(handle_hyp_init)
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/* Install the new exception vectors */
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adrp x6, hyp_vectors
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add x6, x6, :lo12:hyp_vectors
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msr vbar_el2, x6
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/* Set the stack top address */
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mov sp, x1
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/* Use the host VTTBR_EL2 to tell the host and the guests apart */
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mov x9, #VTTBR_HOST
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msr vttbr_el2, x9
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/* Load the base address for the translation tables */
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msr ttbr0_el2, x0
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/* Invalidate the TLB */
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dsb ish
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tlbi alle2
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dsb ishst
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isb
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/* Use the same memory attributes as EL1 */
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mrs x9, mair_el1
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msr mair_el2, x9
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/* Configure address translation */
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msr tcr_el2, x2
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isb
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/* Set the system control register for EL2 */
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msr sctlr_el2, x3
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/* Set the Stage 2 translation control register */
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msr vtcr_el2, x4
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/* Return success */
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mov x0, #0
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/* MMU is up and running */
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ERET
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LEND(handle_hyp_init)
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/*
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* Usage:
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* void vmm_cleanup(uint64_t handle, void *hyp_stub_vectors)
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*
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* Expecting:
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* x1 - physical address of hyp_stub_vectors
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*/
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LENTRY(vmm_cleanup)
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/* Restore the stub vectors */
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msr vbar_el2, x1
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/* Disable the MMU */
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dsb sy
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mrs x2, sctlr_el2
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bic x2, x2, #SCTLR_EL2_M
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msr sctlr_el2, x2
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isb
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ERET
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LEND(vmm_cleanup)
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