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intrng: change multi-interrupt root support type to enum
uint32_t is handy for directly interfacing with assembly-language. For the C portion, enum is much handier. In particular there is no need to count the number of roots by hand. This also works better for being able to build kernels with varying numbers of roots. Switch to INTR_ROOT_COUNT as this better matches the purpose of the value. Switch to root_type, rather than rootnum for similar reasons. Remove the default from the core. Better to require the architectures to declare the type since they will routinely deviate and a default chosen now will likely be suboptimal. Leave intr_irq_handler() taking a register type as that better matches for interfacing with assembly-language.
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d64442a898
commit
536c8d948e
11 changed files with 48 additions and 43 deletions
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@ -200,7 +200,7 @@ gic_cpu_mask(struct arm_gic_softc *sc)
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#ifdef SMP
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static void
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arm_gic_init_secondary(device_t dev, uint32_t rootnum)
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arm_gic_init_secondary(device_t dev, enum root_type root_type)
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{
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struct arm_gic_softc *sc = device_get_softc(dev);
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u_int irq, cpu;
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@ -538,7 +538,7 @@ bcm_lintc_init_pmu_on_ap(struct bcm_lintc_softc *sc, u_int cpu)
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}
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static void
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bcm_lintc_init_secondary(device_t dev, uint32_t rootnum)
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bcm_lintc_init_secondary(device_t dev, enum root_type root_type)
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{
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u_int cpu;
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struct bcm_lintc_softc *sc;
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@ -43,6 +43,12 @@
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#include <dev/ofw/openfirm.h>
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#endif
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enum root_type {
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INTR_ROOT_IRQ = 0,
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INTR_ROOT_COUNT /* MUST BE LAST */
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};
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#ifndef NIRQ
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#define NIRQ 1024 /* XXX - It should be an option. */
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#endif
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@ -1093,7 +1093,7 @@ gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc)
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#ifdef SMP
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static void
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gic_v3_init_secondary(device_t dev, uint32_t rootnum)
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gic_v3_init_secondary(device_t dev, enum root_type root_type)
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{
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struct gic_v3_setup_periph_args pargs;
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device_t child;
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@ -1140,7 +1140,7 @@ gic_v3_init_secondary(device_t dev, uint32_t rootnum)
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for (i = 0; i < sc->gic_nchildren; i++) {
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child = sc->gic_children[i];
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PIC_INIT_SECONDARY(child, rootnum);
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PIC_INIT_SECONDARY(child, root_type);
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}
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}
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@ -1293,7 +1293,7 @@ gicv3_its_setup_intr(device_t dev, struct intr_irqsrc *isrc,
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#ifdef SMP
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static void
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gicv3_its_init_secondary(device_t dev, uint32_t rootnum)
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gicv3_its_init_secondary(device_t dev, enum root_type root_type)
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{
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struct gicv3_its_softc *sc;
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@ -31,6 +31,13 @@
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#include <dev/ofw/openfirm.h>
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#endif
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enum root_type {
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INTR_ROOT_IRQ = 0,
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INTR_ROOT_FIQ = 1,
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INTR_ROOT_COUNT /* MUST BE LAST */
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};
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#include <sys/intr.h>
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#ifndef NIRQ
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@ -48,7 +55,4 @@ arm_irq_memory_barrier(uintptr_t irq)
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#define ACPI_GPIO_XREF 3
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#endif
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#define INTR_ROOT_FIQ 1
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#define INTR_ROOT_NUM 2
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#endif /* _MACHINE_INTR_H */
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@ -74,7 +74,7 @@ CODE {
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}
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static void
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null_pic_init_secondary(device_t dev, uint32_t rootnum)
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null_pic_init_secondary(device_t dev, enum root_type root_type)
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{
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}
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@ -157,7 +157,7 @@ METHOD void pre_ithread {
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METHOD void init_secondary {
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device_t dev;
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uint32_t rootnum;
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enum root_type root_type;
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} DEFAULT null_pic_init_secondary;
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METHOD void ipi_send {
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@ -89,15 +89,6 @@
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#define INTRNAME_LEN (2*MAXCOMLEN + 1)
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/*
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* Archs may define multiple roots with INTR_ROOT_NUM to support different kinds
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* of interrupts (e.g. arm64 FIQs which use a different exception vector than
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* IRQs).
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*/
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#if !defined(INTR_ROOT_NUM)
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#define INTR_ROOT_NUM 1
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#endif
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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@ -115,7 +106,7 @@ struct intr_irq_root {
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void *arg;
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};
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static struct intr_irq_root intr_irq_roots[INTR_ROOT_NUM];
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static struct intr_irq_root intr_irq_roots[INTR_ROOT_COUNT];
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struct intr_pic_child {
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SLIST_ENTRY(intr_pic_child) pc_next;
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@ -337,16 +328,16 @@ isrc_release_counters(struct intr_irqsrc *isrc)
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* from the assembler, where CPU interrupt is served.
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*/
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void
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intr_irq_handler(struct trapframe *tf, uint32_t rootnum)
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intr_irq_handler(struct trapframe *tf, u_register_t root_type)
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{
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struct trapframe * oldframe;
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struct thread * td;
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struct intr_irq_root *root;
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KASSERT(rootnum < INTR_ROOT_NUM,
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("%s: invalid interrupt root %d", __func__, rootnum));
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KASSERT((uintmax_t)root_type < INTR_ROOT_COUNT,
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("%s: invalid interrupt root %ju", __func__, (uintmax_t)root_type));
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root = &intr_irq_roots[rootnum];
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root = &intr_irq_roots[root_type];
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KASSERT(root->filter != NULL, ("%s: no filter", __func__));
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kasan_mark(tf, sizeof(*tf), sizeof(*tf), 0);
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@ -495,11 +486,11 @@ isrc_free_irq(struct intr_irqsrc *isrc)
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}
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device_t
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intr_irq_root_device(uint32_t rootnum)
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intr_irq_root_device(enum root_type root_type)
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{
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KASSERT(rootnum < INTR_ROOT_NUM,
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("%s: invalid interrupt root %d", __func__, rootnum));
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return (intr_irq_roots[rootnum].dev);
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KASSERT((uintmax_t)root_type < INTR_ROOT_COUNT,
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("%s: invalid interrupt root %ju", __func__, (uintmax_t)root_type));
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return (intr_irq_roots[root_type].dev);
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}
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/*
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@ -900,7 +891,7 @@ intr_pic_deregister(device_t dev, intptr_t xref)
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*/
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int
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intr_pic_claim_root(device_t dev, intptr_t xref, intr_irq_filter_t *filter,
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void *arg, uint32_t rootnum)
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void *arg, enum root_type root_type)
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{
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struct intr_pic *pic;
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struct intr_irq_root *root;
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@ -925,9 +916,9 @@ intr_pic_claim_root(device_t dev, intptr_t xref, intr_irq_filter_t *filter,
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* Note that we further suppose that there is not threaded interrupt
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* routine (handler) on the root. See intr_irq_handler().
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*/
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KASSERT(rootnum < INTR_ROOT_NUM,
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("%s: invalid interrupt root %d", __func__, rootnum));
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root = &intr_irq_roots[rootnum];
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KASSERT((uintmax_t)root_type < INTR_ROOT_COUNT,
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("%s: invalid interrupt root %ju", __func__, (uintmax_t)root_type));
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root = &intr_irq_roots[root_type];
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if (root->dev != NULL) {
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device_printf(dev, "another root already set\n");
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return (EBUSY);
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@ -1580,16 +1571,16 @@ void
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intr_pic_init_secondary(void)
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{
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device_t dev;
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uint32_t rootnum;
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enum root_type root_type;
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/*
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* QQQ: Only root PICs are aware of other CPUs ???
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*/
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//mtx_lock(&isrc_table_lock);
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for (rootnum = 0; rootnum < INTR_ROOT_NUM; rootnum++) {
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dev = intr_irq_roots[rootnum].dev;
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for (root_type = 0; root_type < INTR_ROOT_COUNT; root_type++) {
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dev = intr_irq_roots[root_type].dev;
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if (dev != NULL) {
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PIC_INIT_SECONDARY(dev, rootnum);
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PIC_INIT_SECONDARY(dev, root_type);
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}
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}
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//mtx_unlock(&isrc_table_lock);
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@ -35,6 +35,12 @@
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#ifndef _MACHINE_INTR_MACHDEP_H_
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#define _MACHINE_INTR_MACHDEP_H_
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enum root_type {
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INTR_ROOT_IRQ = 0,
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INTR_ROOT_COUNT /* MUST BE LAST */
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};
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#ifndef NIRQ
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#define NIRQ 1024
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#endif
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@ -241,7 +241,7 @@ intc_setup_intr(device_t dev, struct intr_irqsrc *isrc,
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#ifdef SMP
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static void
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intc_init_secondary(device_t dev, uint32_t rootnum)
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intc_init_secondary(device_t dev, enum root_type root_type)
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{
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struct intc_softc *sc;
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struct intr_irqsrc *isrc;
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@ -37,8 +37,6 @@
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#define INTR_IRQ_INVALID 0xFFFFFFFF
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#define INTR_ROOT_IRQ 0
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enum intr_map_data_type {
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INTR_MAP_DATA_ACPI = 0,
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INTR_MAP_DATA_FDT,
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@ -113,12 +111,12 @@ u_int intr_irq_next_cpu(u_int current_cpu, cpuset_t *cpumask);
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struct intr_pic *intr_pic_register(device_t, intptr_t);
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int intr_pic_deregister(device_t, intptr_t);
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int intr_pic_claim_root(device_t, intptr_t, intr_irq_filter_t *, void *,
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uint32_t);
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enum root_type);
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int intr_pic_add_handler(device_t, struct intr_pic *,
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intr_child_irq_filter_t *, void *, uintptr_t, uintptr_t);
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bool intr_is_per_cpu(struct resource *);
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device_t intr_irq_root_device(uint32_t);
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device_t intr_irq_root_device(enum root_type);
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/* Intr interface for BUS. */
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@ -166,7 +164,7 @@ void intr_ipi_send(cpuset_t cpus, u_int ipi);
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void intr_ipi_dispatch(u_int ipi);
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#endif
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/* Main interrupt handler called from asm on most archs except riscv. */
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void intr_irq_handler(struct trapframe *tf, uint32_t rootnum);
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/* Main interrupt handler called from asm on many archs. */
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void intr_irq_handler(struct trapframe *tf, u_register_t root_type);
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#endif /* _SYS_INTR_H */
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