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random: remove hifn(4)
The Hifn 7955 & 7956 only supports deprecated & NIST disallowed algorithms (NIST SP800-224idp): SHA1 and SHA1-HMAC. Furthermore the entropy RNG of the Hifn 7751, 7951, 7811, 7955, and 7956 has no NIST Entropy Source Validation (ESV) certificate and cannot be used in a FIPS-140-3 nor Common Criteara environment. Furthermore the most prolific instance for FreeBSD was the Soekris Engineering vpn1201, vpn1211, vpn1401, and vpn1411 offerings. These are all 32-bit only processors. The i386 kernel was de-supported in 15.0. Reviewed by: jhb Differential Revision: https://reviews.freebsd.org/D53182
This commit is contained in:
David E. O'Brien
parent
86b259a28a
commit
685a78570b
17 changed files with 4 additions and 3871 deletions
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@ -51,6 +51,9 @@
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# xargs -n1 | sort | uniq -d;
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# done
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# 20251028: Remove hifn(4)
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OLD_FILES+=share/man/man4/hifn.4
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# 20251006: Remove libnss_tacplus.a (it never should have been installed)
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OLD_FILES+=usr/lib/libnss_tacplus.a
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@ -1,132 +0,0 @@
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.\" $OpenBSD: hifn.4,v 1.32 2002/09/26 07:55:40 miod Exp $
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.\"
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.\" Copyright (c) 2000 Theo de Raadt
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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.\" WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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.\" DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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.\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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.\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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.\" SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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.\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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.\" ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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.\" POSSIBILITY OF SUCH DAMAGE.
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.\"
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.Dd July 29, 2020
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.Dt HIFN 4
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.Os
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.Sh NAME
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.Nm hifn
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.Nd Hifn 7751/7951/7811/7955/7956 crypto accelerator
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following lines in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device crypto"
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.Cd "device cryptodev"
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.Cd "device hifn"
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.Ed
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.Pp
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Alternatively, to load the driver as a
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module at boot time, place the following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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hifn_load="YES"
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.Ed
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.Sh DESCRIPTION
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The
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.Nm
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driver supports various cards containing the Hifn 7751, 7951,
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7811, 7955, and 7956 chipsets.
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.Pp
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The
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.Nm
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driver registers itself to accelerate
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AES (7955 and 7956 only),
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SHA1, and SHA1-HMAC operations for
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.Xr ipsec 4
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and
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.Xr crypto 4 .
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.Pp
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The Hifn
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.Tn 7951 ,
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.Tn 7811 ,
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.Tn 7955 ,
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and
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.Tn 7956
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will also supply data to the kernel
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.Xr random 4
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subsystem.
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.Sh HARDWARE
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The
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.Nm
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driver supports various cards containing the Hifn 7751, 7951,
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7811, 7955, and 7956
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chipsets, such as:
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.Bl -tag -width namenamenamena -offset indent
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.It Invertex AEON
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No longer being made.
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Came as 128KB SRAM model, or 2MB DRAM model.
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.It Hifn 7751
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Reference board with 512KB SRAM.
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.It PowerCrypt
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Comes with 512KB SRAM.
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.It XL-Crypt
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Only board based on 7811 (which is faster than 7751 and has
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a random number generator).
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.It NetSec 7751
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Supports the most IPsec sessions, with 1MB SRAM.
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.It Soekris Engineering vpn1201 and vpn1211
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See
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.Pa http://www.soekris.com/ .
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Contains a 7951 and supports symmetric and random number operations.
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.It Soekris Engineering vpn1401 and vpn1411
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See
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.Pa http://www.soekris.com/ .
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Contains a 7955 and supports symmetric and random number operations.
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.El
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.Sh SEE ALSO
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.Xr crypto 4 ,
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.Xr intro 4 ,
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.Xr ipsec 4 ,
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.Xr random 4 ,
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.Xr crypto 7 ,
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.Xr crypto 9
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.Sh HISTORY
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The
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.Nm
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device driver appeared in
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.Ox 2.7 .
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The
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.Nm
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device driver was imported to
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.Fx 5.0 .
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.Sh CAVEATS
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The Hifn 9751 shares the same PCI ID.
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This chip is basically a 7751, but with the cryptographic functions missing.
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Instead, the 9751 is only capable of doing compression.
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Since we do not currently attempt to use any of these chips to do
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compression, the 9751-based cards are not useful.
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.Pp
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Support for the 7955 and 7956 is incomplete; the asymmetric crypto
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facilities are to be added and the performance is suboptimal.
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.Sh BUGS
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The 7751 chip starts out at initialization by only supporting compression.
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A proprietary algorithm, which has been reverse engineered, is required to
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unlock the cryptographic functionality of the chip.
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It is possible for vendors to make boards which have a lock ID not known
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to the driver, but all vendors currently just use the obvious ID which is
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13 bytes of 0.
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@ -49,7 +49,6 @@ is received from the device.
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Failures are optionally reported on the console.
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.Sh SEE ALSO
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.Xr crypto 4 ,
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.Xr hifn 4 ,
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.Xr random 4 ,
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.Xr safe 4 ,
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.Xr crypto 9
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@ -2655,10 +2655,6 @@ device rndtest # FIPS 140-2 entropy tester
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device ccr # Chelsio T6
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device hifn # Hifn 7951, 7781, etc.
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options HIFN_DEBUG # enable debugging support: hw.hifn.debug
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options HIFN_RNDTEST # enable rndtest support
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device safe # SafeNet 1141
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options SAFE_DEBUG # enable debugging support: hw.safe.debug
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options SAFE_RNDTEST # enable rndtest support
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@ -1782,7 +1782,6 @@ dev/hid/ietp.c optional ietp
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dev/hid/ps4dshock.c optional ps4dshock
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dev/hid/u2f.c optional u2f
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dev/hid/xb360gp.c optional xb360gp
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dev/hifn/hifn7751.c optional hifn
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dev/hptiop/hptiop.c optional hptiop scbus
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dev/hwpmc/hwpmc_logging.c optional hwpmc
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dev/hwpmc/hwpmc_mod.c optional hwpmc
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@ -736,10 +736,6 @@ BCE_NVRAM_WRITE_SUPPORT opt_bce.h
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SOCKBUF_DEBUG opt_global.h
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# options for hifn driver
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HIFN_DEBUG opt_hifn.h
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HIFN_RNDTEST opt_hifn.h
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# options for safenet driver
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SAFE_DEBUG opt_safe.h
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SAFE_NO_RNG opt_safe.h
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File diff suppressed because it is too large
Load diff
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@ -1,542 +0,0 @@
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/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Invertex AEON / Hifn 7751 driver
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* Copyright (c) 1999 Invertex Inc. All rights reserved.
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* Copyright (c) 1999 Theo de Raadt
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* Copyright (c) 2000-2001 Network Security Technologies, Inc.
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* http://www.netsec.net
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*
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* Please send any comments, feedback, bug-fixes, or feature requests to
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* software@invertex.com.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Effort sponsored in part by the Defense Advanced Research Projects
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* Agency (DARPA) and Air Force Research Laboratory, Air Force
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* Materiel Command, USAF, under agreement number F30602-01-2-0537.
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*
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*/
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#ifndef __HIFN_H__
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#define __HIFN_H__
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#include <sys/endian.h>
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/*
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* Some PCI configuration space offset defines. The names were made
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* identical to the names used by the Linux kernel.
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*/
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#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */
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#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */
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#define HIFN_TRDY_TIMEOUT 0x40
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#define HIFN_RETRY_TIMEOUT 0x41
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/*
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* PCI vendor and device identifiers
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* (the names are preserved from their OpenBSD source).
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*/
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#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */
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#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */
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#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */
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#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */
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#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */
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#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */
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#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */
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#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */
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#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */
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#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */
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#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */
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/*
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* The values below should multiple of 4 -- and be large enough to handle
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* any command the driver implements.
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*
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* MAX_COMMAND = base command + mac command + encrypt command +
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* mac-key + rc4-key
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* MAX_RESULT = base result + mac result + mac + encrypt result
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*
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*
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*/
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#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
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#define HIFN_MAX_RESULT (8 + 4 + 20 + 4)
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/*
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* hifn_desc_t
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*
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* Holds an individual descriptor for any of the rings.
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*/
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typedef struct hifn_desc {
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volatile u_int32_t l; /* length and status bits */
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volatile u_int32_t p;
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} hifn_desc_t;
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/*
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* Masks for the "length" field of struct hifn_desc.
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*/
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#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */
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#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */
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#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */
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#define HIFN_D_OVER 0x08000000 /* overflow */
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#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */
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#define HIFN_D_JUMP 0x40000000 /* jump descriptor */
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#define HIFN_D_VALID 0x80000000 /* valid bit */
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/*
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* Processing Unit Registers (offset from BASEREG0)
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*/
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#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
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#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
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#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
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#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
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#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
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#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
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#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
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#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
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#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */
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#define HIFN_0_MUTE1 0x80
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#define HIFN_0_MUTE2 0x90
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#define HIFN_0_SPACESIZE 0x100 /* Register space size */
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/* Processing Unit Control Register (HIFN_0_PUCTRL) */
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#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
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#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
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#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
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#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
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#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
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/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
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#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
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#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
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#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
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#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
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#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
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#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
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#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
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#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
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#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
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#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
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/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
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#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
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#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
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#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
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#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
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#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
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#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
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#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
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#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
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#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
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#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
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#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
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#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
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#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
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#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
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#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
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#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
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#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
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#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
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#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
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#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
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#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
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#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
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#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
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/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
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#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
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#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
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#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
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#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
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#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
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#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
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#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
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#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
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#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
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#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
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/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
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#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
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#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
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#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
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#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
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#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
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#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
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#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
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#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
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#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
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#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
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#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
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#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
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#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
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#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
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#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
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#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
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#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
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|
||||
/* FIFO Status Register (HIFN_0_FIFOSTAT) */
|
||||
#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
|
||||
#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
|
||||
|
||||
/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
|
||||
#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */
|
||||
|
||||
/*
|
||||
* DMA Interface Registers (offset from BASEREG1)
|
||||
*/
|
||||
#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
|
||||
#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
|
||||
#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
|
||||
#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
|
||||
#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
|
||||
#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
|
||||
#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
|
||||
#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */
|
||||
#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
|
||||
#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
|
||||
#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
|
||||
#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
|
||||
#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */
|
||||
#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
|
||||
#define HIFN_1_REVID 0x98 /* Revision ID */
|
||||
|
||||
#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
|
||||
#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
|
||||
#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */
|
||||
#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */
|
||||
#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */
|
||||
#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
|
||||
#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
|
||||
#define HIFN_1_RNG_DATA 0x318 /* RNG data */
|
||||
#define HIFN_1_PUB_MODE 0x320 /* PK mode */
|
||||
#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */
|
||||
#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */
|
||||
#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
|
||||
#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
|
||||
|
||||
/* DMA Status and Control Register (HIFN_1_DMA_CSR) */
|
||||
#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
|
||||
#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
|
||||
#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
|
||||
#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
|
||||
#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
|
||||
#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
|
||||
#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
|
||||
#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
|
||||
#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
|
||||
#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
|
||||
#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
|
||||
#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
|
||||
#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
|
||||
#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
|
||||
#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
|
||||
#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
|
||||
#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
|
||||
#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
|
||||
#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
|
||||
#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
|
||||
#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
|
||||
#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
|
||||
#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
|
||||
#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
|
||||
#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
|
||||
#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
|
||||
#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
|
||||
#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
|
||||
#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
|
||||
#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
|
||||
#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
|
||||
#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
|
||||
#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
|
||||
#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
|
||||
#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
|
||||
#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
|
||||
#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
|
||||
#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
|
||||
|
||||
/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
|
||||
#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
|
||||
#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
|
||||
#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
|
||||
#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
|
||||
#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
|
||||
#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
|
||||
#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
|
||||
#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
|
||||
#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
|
||||
#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
|
||||
#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
|
||||
#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
|
||||
#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
|
||||
#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
|
||||
#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
|
||||
#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
|
||||
#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
|
||||
#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
|
||||
#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
|
||||
#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
|
||||
#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
|
||||
#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
|
||||
|
||||
/* DMA Configuration Register (HIFN_1_DMA_CNFG) */
|
||||
#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
|
||||
#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
|
||||
#define HIFN_DMACNFG_UNLOCK 0x00000800
|
||||
#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
|
||||
#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
|
||||
#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
|
||||
#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
|
||||
#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
|
||||
|
||||
/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */
|
||||
#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */
|
||||
#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */
|
||||
#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */
|
||||
#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */
|
||||
#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12
|
||||
#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8
|
||||
#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4
|
||||
#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0
|
||||
|
||||
/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */
|
||||
#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */
|
||||
|
||||
/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */
|
||||
#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */
|
||||
#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */
|
||||
#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */
|
||||
|
||||
/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */
|
||||
#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */
|
||||
#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */
|
||||
|
||||
/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */
|
||||
#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */
|
||||
#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */
|
||||
#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */
|
||||
#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */
|
||||
#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */
|
||||
#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */
|
||||
#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */
|
||||
#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */
|
||||
#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */
|
||||
|
||||
/* Public key reset register (HIFN_1_PUB_RESET) */
|
||||
#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
|
||||
|
||||
/* Public operation register (HIFN_1_PUB_OP) */
|
||||
#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */
|
||||
#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */
|
||||
#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */
|
||||
#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
|
||||
#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
|
||||
#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
|
||||
#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
|
||||
#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
|
||||
#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
|
||||
#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
|
||||
#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
|
||||
#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
|
||||
#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
|
||||
#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
|
||||
#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
|
||||
#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */
|
||||
#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */
|
||||
|
||||
/* Public operand length register (HIFN_1_PUB_OPLEN) */
|
||||
#define HIFN_PUBOPLEN_MODLEN 0x0000007f
|
||||
#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80
|
||||
#define HIFN_PUBOPLEN_REDLEN 0x003c0000
|
||||
|
||||
/* Public status register (HIFN_1_PUB_STATUS) */
|
||||
#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
|
||||
#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
|
||||
#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */
|
||||
#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */
|
||||
#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */
|
||||
#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */
|
||||
#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */
|
||||
|
||||
/* Public interrupt enable register (HIFN_1_PUB_IEN) */
|
||||
#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
|
||||
|
||||
/* Random number generator config register (HIFN_1_RNG_CONFIG) */
|
||||
#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
|
||||
|
||||
/*
|
||||
* Register offsets in register set 1
|
||||
*/
|
||||
|
||||
#define HIFN_UNLOCK_SECRET1 0xf4
|
||||
#define HIFN_UNLOCK_SECRET2 0xfc
|
||||
|
||||
/*
|
||||
* PLL config register
|
||||
*
|
||||
* This register is present only on 7954/7955/7956 parts. It must be
|
||||
* programmed according to the bus interface method used by the h/w.
|
||||
* Note that the parts require a stable clock. Since the PCI clock
|
||||
* may vary the reference clock must usually be used. To avoid
|
||||
* overclocking the core logic, setup must be done carefully, refer
|
||||
* to the driver for details. The exact multiplier required varies
|
||||
* by part and system configuration; refer to the Hifn documentation.
|
||||
*/
|
||||
#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */
|
||||
#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */
|
||||
/* bit 2 reserved */
|
||||
#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */
|
||||
#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */
|
||||
/* bits 5-9 reserved */
|
||||
#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */
|
||||
#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */
|
||||
#define HIFN_PLL_ND_SHIFT 11
|
||||
#define HIFN_PLL_ND_2 0x00000000 /* 2x */
|
||||
#define HIFN_PLL_ND_4 0x00000800 /* 4x */
|
||||
#define HIFN_PLL_ND_6 0x00001000 /* 6x */
|
||||
#define HIFN_PLL_ND_8 0x00001800 /* 8x */
|
||||
#define HIFN_PLL_ND_10 0x00002000 /* 10x */
|
||||
#define HIFN_PLL_ND_12 0x00002800 /* 12x */
|
||||
/* bits 14-15 reserved */
|
||||
#define HIFN_PLL_IS 0x00010000 /* charge pump current select */
|
||||
/* bits 17-31 reserved */
|
||||
|
||||
/*
|
||||
* Board configuration specifies only these bits.
|
||||
*/
|
||||
#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL)
|
||||
|
||||
/*
|
||||
* Public Key Engine Mode Register
|
||||
*/
|
||||
#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */
|
||||
#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* Structs for board commands
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/*
|
||||
* Structure to help build up the command data structure.
|
||||
*/
|
||||
typedef struct hifn_base_command {
|
||||
volatile u_int16_t masks;
|
||||
volatile u_int16_t session_num;
|
||||
volatile u_int16_t total_source_count;
|
||||
volatile u_int16_t total_dest_count;
|
||||
} hifn_base_command_t;
|
||||
|
||||
#define HIFN_BASE_CMD_MAC 0x0400
|
||||
#define HIFN_BASE_CMD_CRYPT 0x0800
|
||||
#define HIFN_BASE_CMD_DECODE 0x2000
|
||||
#define HIFN_BASE_CMD_SRCLEN_M 0xc000
|
||||
#define HIFN_BASE_CMD_SRCLEN_S 14
|
||||
#define HIFN_BASE_CMD_DSTLEN_M 0x3000
|
||||
#define HIFN_BASE_CMD_DSTLEN_S 12
|
||||
#define HIFN_BASE_CMD_LENMASK_HI 0x30000
|
||||
#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
|
||||
|
||||
/*
|
||||
* Structure to help build up the command data structure.
|
||||
*/
|
||||
typedef struct hifn_crypt_command {
|
||||
volatile u_int16_t masks;
|
||||
volatile u_int16_t header_skip;
|
||||
volatile u_int16_t source_count;
|
||||
volatile u_int16_t reserved;
|
||||
} hifn_crypt_command_t;
|
||||
|
||||
#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
|
||||
#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
|
||||
#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
|
||||
#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
|
||||
#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
|
||||
#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
|
||||
#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
|
||||
#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
|
||||
#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
|
||||
#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
|
||||
#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
|
||||
#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
|
||||
#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
|
||||
|
||||
#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
|
||||
#define HIFN_CRYPT_CMD_SRCLEN_S 14
|
||||
|
||||
#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
|
||||
#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
|
||||
#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
|
||||
#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
|
||||
|
||||
/*
|
||||
* Structure to help build up the command data structure.
|
||||
*/
|
||||
typedef struct hifn_mac_command {
|
||||
volatile u_int16_t masks;
|
||||
volatile u_int16_t header_skip;
|
||||
volatile u_int16_t source_count;
|
||||
volatile u_int16_t reserved;
|
||||
} hifn_mac_command_t;
|
||||
|
||||
#define HIFN_MAC_CMD_ALG_MASK 0x0001
|
||||
#define HIFN_MAC_CMD_ALG_SHA1 0x0000
|
||||
#define HIFN_MAC_CMD_ALG_MD5 0x0001
|
||||
#define HIFN_MAC_CMD_MODE_MASK 0x000c
|
||||
#define HIFN_MAC_CMD_MODE_HMAC 0x0000
|
||||
#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
|
||||
#define HIFN_MAC_CMD_MODE_HASH 0x0008
|
||||
#define HIFN_MAC_CMD_MODE_FULL 0x0004
|
||||
#define HIFN_MAC_CMD_TRUNC 0x0010
|
||||
#define HIFN_MAC_CMD_RESULT 0x0020
|
||||
#define HIFN_MAC_CMD_APPEND 0x0040
|
||||
#define HIFN_MAC_CMD_SRCLEN_M 0xc000
|
||||
#define HIFN_MAC_CMD_SRCLEN_S 14
|
||||
|
||||
/*
|
||||
* MAC POS IPsec initiates authentication after encryption on encodes
|
||||
* and before decryption on decodes.
|
||||
*/
|
||||
#define HIFN_MAC_CMD_POS_IPSEC 0x0200
|
||||
#define HIFN_MAC_CMD_NEW_KEY 0x0800
|
||||
|
||||
/*
|
||||
* The poll frequency and poll scalar defines are unshifted values used
|
||||
* to set fields in the DMA Configuration Register.
|
||||
*/
|
||||
#ifndef HIFN_POLL_FREQUENCY
|
||||
#define HIFN_POLL_FREQUENCY 0x1
|
||||
#endif
|
||||
|
||||
#ifndef HIFN_POLL_SCALAR
|
||||
#define HIFN_POLL_SCALAR 0x0
|
||||
#endif
|
||||
|
||||
#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
|
||||
#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
|
||||
#endif /* __HIFN_H__ */
|
||||
|
|
@ -1,346 +0,0 @@
|
|||
/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */
|
||||
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Invertex AEON / Hifn 7751 driver
|
||||
* Copyright (c) 1999 Invertex Inc. All rights reserved.
|
||||
* Copyright (c) 1999 Theo de Raadt
|
||||
* Copyright (c) 2000-2001 Network Security Technologies, Inc.
|
||||
* http://www.netsec.net
|
||||
*
|
||||
* Please send any comments, feedback, bug-fixes, or feature requests to
|
||||
* software@invertex.com.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Effort sponsored in part by the Defense Advanced Research Projects
|
||||
* Agency (DARPA) and Air Force Research Laboratory, Air Force
|
||||
* Materiel Command, USAF, under agreement number F30602-01-2-0537.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __HIFN7751VAR_H__
|
||||
#define __HIFN7751VAR_H__
|
||||
|
||||
#ifdef _KERNEL
|
||||
|
||||
/*
|
||||
* Some configurable values for the driver. By default command+result
|
||||
* descriptor rings are the same size. The src+dst descriptor rings
|
||||
* are sized at 3.5x the number of potential commands. Slower parts
|
||||
* (e.g. 7951) tend to run out of src descriptors; faster parts (7811)
|
||||
* src+cmd/result descriptors. It's not clear that increasing the size
|
||||
* of the descriptor rings helps performance significantly as other
|
||||
* factors tend to come into play (e.g. copying misaligned packets).
|
||||
*/
|
||||
#define HIFN_D_CMD_RSIZE 24 /* command descriptors */
|
||||
#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */
|
||||
#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */
|
||||
#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */
|
||||
|
||||
/*
|
||||
* Length values for cryptography
|
||||
*/
|
||||
#define HIFN_DES_KEY_LENGTH 8
|
||||
#define HIFN_3DES_KEY_LENGTH 24
|
||||
#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH
|
||||
#define HIFN_IV_LENGTH 8
|
||||
#define HIFN_AES_IV_LENGTH 16
|
||||
#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
|
||||
|
||||
/*
|
||||
* Length values for authentication
|
||||
*/
|
||||
#define HIFN_MAC_KEY_LENGTH 64
|
||||
#define HIFN_MD5_LENGTH 16
|
||||
#define HIFN_SHA1_LENGTH 20
|
||||
#define HIFN_MAC_TRUNC_LENGTH 12
|
||||
|
||||
#define MAX_SCATTER 64
|
||||
|
||||
/*
|
||||
* Data structure to hold all 4 rings and any other ring related data
|
||||
* that should reside in DMA.
|
||||
*/
|
||||
struct hifn_dma {
|
||||
/*
|
||||
* Descriptor rings. We add +1 to the size to accomidate the
|
||||
* jump descriptor.
|
||||
*/
|
||||
struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1];
|
||||
struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1];
|
||||
struct hifn_desc dstr[HIFN_D_DST_RSIZE+1];
|
||||
struct hifn_desc resr[HIFN_D_RES_RSIZE+1];
|
||||
|
||||
|
||||
u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
|
||||
u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
|
||||
u_int32_t slop[HIFN_D_CMD_RSIZE];
|
||||
u_int64_t test_src, test_dst;
|
||||
} ;
|
||||
|
||||
|
||||
struct hifn_session {
|
||||
int hs_mlen;
|
||||
};
|
||||
|
||||
#define HIFN_RING_SYNC(sc, r, i, f) \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f))
|
||||
|
||||
#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f))
|
||||
#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f))
|
||||
#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f))
|
||||
#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f))
|
||||
|
||||
#define HIFN_CMD_SYNC(sc, i, f) \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f))
|
||||
|
||||
#define HIFN_RES_SYNC(sc, i, f) \
|
||||
bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f))
|
||||
|
||||
/*
|
||||
* Holds data specific to a single HIFN board.
|
||||
*/
|
||||
struct hifn_softc {
|
||||
device_t sc_dev; /* device backpointer */
|
||||
struct mtx sc_mtx; /* per-instance lock */
|
||||
bus_dma_tag_t sc_dmat; /* parent DMA tag descriptor */
|
||||
struct resource *sc_bar0res;
|
||||
bus_space_handle_t sc_sh0; /* bar0 bus space handle */
|
||||
bus_space_tag_t sc_st0; /* bar0 bus space tag */
|
||||
bus_size_t sc_bar0_lastreg;/* bar0 last reg written */
|
||||
struct resource *sc_bar1res;
|
||||
bus_space_handle_t sc_sh1; /* bar1 bus space handle */
|
||||
bus_space_tag_t sc_st1; /* bar1 bus space tag */
|
||||
bus_size_t sc_bar1_lastreg;/* bar1 last reg written */
|
||||
struct resource *sc_irq;
|
||||
void *sc_intrhand; /* interrupt handle */
|
||||
|
||||
u_int32_t sc_dmaier;
|
||||
u_int32_t sc_drammodel; /* 1=dram, 0=sram */
|
||||
u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */
|
||||
|
||||
struct hifn_dma *sc_dma;
|
||||
bus_dmamap_t sc_dmamap;
|
||||
bus_dma_segment_t sc_dmasegs[1];
|
||||
bus_addr_t sc_dma_physaddr;/* physical address of sc_dma */
|
||||
int sc_dmansegs;
|
||||
struct hifn_command *sc_hifn_commands[HIFN_D_RES_RSIZE];
|
||||
/*
|
||||
* Our current positions for insertion and removal from the desriptor
|
||||
* rings.
|
||||
*/
|
||||
int sc_cmdi, sc_srci, sc_dsti, sc_resi;
|
||||
volatile int sc_cmdu, sc_srcu, sc_dstu, sc_resu;
|
||||
int sc_cmdk, sc_srck, sc_dstk, sc_resk;
|
||||
|
||||
int32_t sc_cid;
|
||||
uint16_t sc_ena;
|
||||
int sc_maxses;
|
||||
int sc_ramsize;
|
||||
int sc_flags;
|
||||
#define HIFN_HAS_RNG 0x1 /* includes random number generator */
|
||||
#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */
|
||||
#define HIFN_HAS_AES 0x4 /* includes AES support */
|
||||
#define HIFN_IS_7811 0x8 /* Hifn 7811 part */
|
||||
#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */
|
||||
struct callout sc_rngto; /* for polling RNG */
|
||||
struct callout sc_tickto; /* for managing DMA */
|
||||
int sc_rngfirst;
|
||||
int sc_rnghz; /* RNG polling frequency */
|
||||
struct rndtest_state *sc_rndtest; /* RNG test state */
|
||||
void (*sc_harvest)(struct rndtest_state *,
|
||||
void *, u_int);
|
||||
int sc_c_busy; /* command ring busy */
|
||||
int sc_s_busy; /* source data ring busy */
|
||||
int sc_d_busy; /* destination data ring busy */
|
||||
int sc_r_busy; /* result ring busy */
|
||||
int sc_active; /* for initial countdown */
|
||||
int sc_needwakeup; /* ops q'd wating on resources */
|
||||
int sc_curbatch; /* # ops submitted w/o int */
|
||||
int sc_suspended;
|
||||
#ifdef HIFN_VULCANDEV
|
||||
struct cdev *sc_pkdev;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define HIFN_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
|
||||
#define HIFN_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
|
||||
|
||||
/*
|
||||
* hifn_command_t
|
||||
*
|
||||
* This is the control structure used to pass commands to hifn_encrypt().
|
||||
*
|
||||
* flags
|
||||
* -----
|
||||
* Flags is the bitwise "or" values for command configuration. A single
|
||||
* encrypt direction needs to be set:
|
||||
*
|
||||
* HIFN_ENCODE or HIFN_DECODE
|
||||
*
|
||||
* To use cryptography, a single crypto algorithm must be included:
|
||||
*
|
||||
* HIFN_CRYPT_3DES or HIFN_CRYPT_DES
|
||||
*
|
||||
* To use authentication is used, a single MAC algorithm must be included:
|
||||
*
|
||||
* HIFN_MAC_MD5 or HIFN_MAC_SHA1
|
||||
*
|
||||
* By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash.
|
||||
* If the value below is set, hash values are truncated or assumed
|
||||
* truncated to 12 bytes:
|
||||
*
|
||||
* HIFN_MAC_TRUNC
|
||||
*
|
||||
* Keys for encryption and authentication can be sent as part of a command,
|
||||
* or the last key value used with a particular session can be retrieved
|
||||
* and used again if either of these flags are not specified.
|
||||
*
|
||||
* HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY
|
||||
*
|
||||
* session_num
|
||||
* -----------
|
||||
* A number between 0 and 2048 (for DRAM models) or a number between
|
||||
* 0 and 768 (for SRAM models). Those who don't want to use session
|
||||
* numbers should leave value at zero and send a new crypt key and/or
|
||||
* new MAC key on every command. If you use session numbers and
|
||||
* don't send a key with a command, the last key sent for that same
|
||||
* session number will be used.
|
||||
*
|
||||
* Warning: Using session numbers and multiboard at the same time
|
||||
* is currently broken.
|
||||
*
|
||||
* mbuf
|
||||
* ----
|
||||
* Either fill in the mbuf pointer and npa=0 or
|
||||
* fill packp[] and packl[] and set npa to > 0
|
||||
*
|
||||
* mac_header_skip
|
||||
* ---------------
|
||||
* The number of bytes of the source_buf that are skipped over before
|
||||
* authentication begins. This must be a number between 0 and 2^16-1
|
||||
* and can be used by IPsec implementers to skip over IP headers.
|
||||
* *** Value ignored if authentication not used ***
|
||||
*
|
||||
* crypt_header_skip
|
||||
* -----------------
|
||||
* The number of bytes of the source_buf that are skipped over before
|
||||
* the cryptographic operation begins. This must be a number between 0
|
||||
* and 2^16-1. For IPsec, this number will always be 8 bytes larger
|
||||
* than the auth_header_skip (to skip over the ESP header).
|
||||
* *** Value ignored if cryptography not used ***
|
||||
*
|
||||
*/
|
||||
struct hifn_operand {
|
||||
bus_dmamap_t map;
|
||||
bus_size_t mapsize;
|
||||
int nsegs;
|
||||
bus_dma_segment_t segs[MAX_SCATTER];
|
||||
};
|
||||
struct hifn_command {
|
||||
struct hifn_session *session;
|
||||
u_int16_t base_masks, cry_masks, mac_masks;
|
||||
u_int8_t iv[HIFN_MAX_IV_LENGTH], mac[HIFN_MAC_KEY_LENGTH];
|
||||
const uint8_t *ck;
|
||||
int cklen;
|
||||
int sloplen, slopidx;
|
||||
|
||||
struct hifn_operand src;
|
||||
struct hifn_operand dst;
|
||||
struct mbuf *dst_m;
|
||||
|
||||
struct hifn_softc *softc;
|
||||
struct cryptop *crp;
|
||||
};
|
||||
|
||||
#define src_map src.map
|
||||
#define src_mapsize src.mapsize
|
||||
#define src_segs src.segs
|
||||
#define src_nsegs src.nsegs
|
||||
|
||||
#define dst_map dst.map
|
||||
#define dst_mapsize dst.mapsize
|
||||
#define dst_segs dst.segs
|
||||
#define dst_nsegs dst.nsegs
|
||||
|
||||
/*
|
||||
* Return values for hifn_crypto()
|
||||
*/
|
||||
#define HIFN_CRYPTO_SUCCESS 0
|
||||
#define HIFN_CRYPTO_BAD_INPUT (-1)
|
||||
#define HIFN_CRYPTO_RINGS_FULL (-2)
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* Function: hifn_crypto
|
||||
*
|
||||
* Purpose: Called by external drivers to begin an encryption on the
|
||||
* HIFN board.
|
||||
*
|
||||
* Blocking/Non-blocking Issues
|
||||
* ============================
|
||||
* The driver cannot block in hifn_crypto (no calls to tsleep) currently.
|
||||
* hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough
|
||||
* room in any of the rings for the request to proceed.
|
||||
*
|
||||
* Return Values
|
||||
* =============
|
||||
* 0 for success, negative values on error
|
||||
*
|
||||
* Defines for negative error codes are:
|
||||
*
|
||||
* HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings.
|
||||
* HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking
|
||||
* behaviour was requested.
|
||||
*
|
||||
*************************************************************************/
|
||||
#endif /* _KERNEL */
|
||||
|
||||
struct hifn_stats {
|
||||
u_int64_t hst_ibytes;
|
||||
u_int64_t hst_obytes;
|
||||
u_int32_t hst_ipackets;
|
||||
u_int32_t hst_opackets;
|
||||
u_int32_t hst_invalid;
|
||||
u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */
|
||||
u_int32_t hst_abort;
|
||||
u_int32_t hst_noirq; /* IRQ for no reason */
|
||||
u_int32_t hst_totbatch; /* ops submitted w/o interrupt */
|
||||
u_int32_t hst_maxbatch; /* max ops submitted together */
|
||||
u_int32_t hst_unaligned; /* unaligned src caused copy */
|
||||
/*
|
||||
* The following divides hst_nomem into more specific buckets.
|
||||
*/
|
||||
u_int32_t hst_nomem_map; /* bus_dmamap_create failed */
|
||||
u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */
|
||||
u_int32_t hst_nomem_mbuf; /* MGET* failed */
|
||||
u_int32_t hst_nomem_mcl; /* MCLGET* failed */
|
||||
u_int32_t hst_nomem_cr; /* out of command/result descriptor */
|
||||
u_int32_t hst_nomem_sd; /* out of src/dst descriptors */
|
||||
};
|
||||
|
||||
#endif /* __HIFN7751VAR_H__ */
|
||||
|
|
@ -173,9 +173,6 @@ static const struct fxrng_ent_char {
|
|||
[RANDOM_PURE_GLXSB] = {
|
||||
.entc_cls = &fxrng_hi_push,
|
||||
},
|
||||
[RANDOM_PURE_HIFN] = {
|
||||
.entc_cls = &fxrng_hi_push,
|
||||
},
|
||||
[RANDOM_PURE_RDRAND] = {
|
||||
.entc_cls = &fxrng_hi_pull,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -663,7 +663,6 @@ static const char *random_source_descr[ENTROPYSOURCE] = {
|
|||
[RANDOM_RANDOMDEV] = "RANDOMDEV", /* ENVIRONMENTAL_END */
|
||||
[RANDOM_PURE_SAFE] = "PURE_SAFE", /* PURE_START */
|
||||
[RANDOM_PURE_GLXSB] = "PURE_GLXSB",
|
||||
[RANDOM_PURE_HIFN] = "PURE_HIFN",
|
||||
[RANDOM_PURE_RDRAND] = "PURE_RDRAND",
|
||||
[RANDOM_PURE_RDSEED] = "PURE_RDSEED",
|
||||
[RANDOM_PURE_NEHEMIAH] = "PURE_NEHEMIAH",
|
||||
|
|
|
|||
|
|
@ -135,7 +135,6 @@ SUBDIR= \
|
|||
gpio \
|
||||
${_gve} \
|
||||
hid \
|
||||
hifn \
|
||||
${_hpt27xx} \
|
||||
${_hptiop} \
|
||||
${_hptmv} \
|
||||
|
|
|
|||
|
|
@ -1,12 +0,0 @@
|
|||
.PATH: ${SRCTOP}/sys/dev/hifn
|
||||
KMOD = hifn
|
||||
SRCS = hifn7751.c opt_hifn.h
|
||||
SRCS += device_if.h bus_if.h pci_if.h
|
||||
SRCS += opt_bus.h cryptodev_if.h
|
||||
|
||||
.if !defined(KERNBUILDDIR)
|
||||
opt_hifn.h:
|
||||
echo "#define HIFN_DEBUG 1" > ${.TARGET}
|
||||
.endif
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
|
@ -91,7 +91,6 @@ enum random_entropy_source {
|
|||
RANDOM_PURE_START,
|
||||
RANDOM_PURE_SAFE = RANDOM_PURE_START,
|
||||
RANDOM_PURE_GLXSB,
|
||||
RANDOM_PURE_HIFN,
|
||||
RANDOM_PURE_RDRAND,
|
||||
RANDOM_PURE_RDSEED,
|
||||
RANDOM_PURE_NEHEMIAH,
|
||||
|
|
|
|||
|
|
@ -1,19 +0,0 @@
|
|||
# Doxyfile 1.5.2
|
||||
|
||||
#---------------------------------------------------------------------------
|
||||
# Project related configuration options
|
||||
#---------------------------------------------------------------------------
|
||||
PROJECT_NAME = "FreeBSD kernel HIFN device code"
|
||||
OUTPUT_DIRECTORY = $(DOXYGEN_DEST_PATH)/dev_hifn/
|
||||
EXTRACT_ALL = YES # for undocumented src, no warnings enabled
|
||||
#---------------------------------------------------------------------------
|
||||
# configuration options related to the input files
|
||||
#---------------------------------------------------------------------------
|
||||
INPUT = $(DOXYGEN_SRC_PATH)/dev/hifn/ \
|
||||
$(NOTREVIEWED)
|
||||
|
||||
GENERATE_TAGFILE = dev_hifn/dev_hifn.tag
|
||||
|
||||
@INCLUDE_PATH = $(DOXYGEN_INCLUDE_PATH)
|
||||
@INCLUDE = common-Doxyfile
|
||||
|
||||
|
|
@ -25,7 +25,7 @@
|
|||
# SUCH DAMAGE.
|
||||
#
|
||||
|
||||
PROGS= cryptocheck cryptostats hifnstats ipsecstats safestats
|
||||
PROGS= cryptocheck cryptostats ipsecstats safestats
|
||||
MAN=
|
||||
BINDIR?= /usr/local/bin
|
||||
|
||||
|
|
@ -33,7 +33,6 @@ BINDIR?= /usr/local/bin
|
|||
LIBADD.cryptocheck+= crypto util
|
||||
|
||||
# cryptostats: dump statistics kept by the core crypto code
|
||||
# hifnstats: print statistics kept by the HIFN driver
|
||||
# safestats: statistics kept by the SafeNet driver
|
||||
# ipsecstats: print statistics kept by fast ipsec
|
||||
|
||||
|
|
|
|||
|
|
@ -1,63 +0,0 @@
|
|||
/*-
|
||||
* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/sysctl.h>
|
||||
|
||||
#include <err.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "../../../sys/dev/hifn/hifn7751var.h"
|
||||
|
||||
/*
|
||||
* Little program to dump the statistics block for the hifn driver.
|
||||
*/
|
||||
int
|
||||
main(int argc, char *argv[])
|
||||
{
|
||||
struct hifn_stats stats;
|
||||
size_t slen;
|
||||
|
||||
slen = sizeof (stats);
|
||||
if (sysctlbyname("hw.hifn.stats", &stats, &slen, NULL, 0) < 0)
|
||||
err(1, "kern.hifn.stats");
|
||||
|
||||
printf("input %llu bytes %u packets\n",
|
||||
stats.hst_ibytes, stats.hst_ipackets);
|
||||
printf("output %llu bytes %u packets\n",
|
||||
stats.hst_obytes, stats.hst_opackets);
|
||||
printf("invalid %u nomem %u abort %u\n",
|
||||
stats.hst_invalid, stats.hst_nomem, stats.hst_abort);
|
||||
printf("noirq %u unaligned %u\n",
|
||||
stats.hst_noirq, stats.hst_unaligned);
|
||||
printf("totbatch %u maxbatch %u\n",
|
||||
stats.hst_totbatch, stats.hst_maxbatch);
|
||||
printf("nomem: map %u load %u mbuf %u mcl %u cr %u sd %u\n",
|
||||
stats.hst_nomem_map, stats.hst_nomem_load,
|
||||
stats.hst_nomem_mbuf, stats.hst_nomem_mcl,
|
||||
stats.hst_nomem_cr, stats.hst_nomem_sd);
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue