qat: enable qat driver for 402xx device

Enabled qat driver support for 402xx device with
ID 0x4944/0x4945. This is an additional device supported
under the existing qat_4xxx driver. Firmwares specific to
the 402xx device are added.

Signed-off-by: Hareshx Sankar Raj <hareshx.sankar.raj@intel.com>

Relnotes:	yes
Sponsored by:	Intel Corporation
MFC after:	1 month
Differential Revision:	https://reviews.freebsd.org/D52488
This commit is contained in:
Hareshx Sankar Raj 2025-09-04 14:21:36 -04:00 committed by Mark Johnston
parent 226375a1f6
commit 7fbd362c09
10 changed files with 78 additions and 28 deletions

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@ -39,12 +39,16 @@
#define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941
#define ADF_401XX_PCI_DEVICE_ID 0x4942
#define ADF_401XXIOV_PCI_DEVICE_ID 0x4943
#define ADF_402XX_PCI_DEVICE_ID 0x4944
#define ADF_402XXIOV_PCI_DEVICE_ID 0x4945
#define IS_QAT_GEN3(ID) ({ (ID == ADF_C4XXX_PCI_DEVICE_ID); })
static inline bool
IS_QAT_GEN4(const unsigned int id)
{
return (id == ADF_4XXX_PCI_DEVICE_ID || id == ADF_401XX_PCI_DEVICE_ID ||
id == ADF_402XX_PCI_DEVICE_ID ||
id == ADF_402XXIOV_PCI_DEVICE_ID ||
id == ADF_4XXXIOV_PCI_DEVICE_ID ||
id == ADF_401XXIOV_PCI_DEVICE_ID);
}

View file

@ -26,7 +26,7 @@
/* Part name and number of the accelerator device */
#define SAL_INFO2_DRIVER_SW_VERSION_MAJ_NUMBER 3
#define SAL_INFO2_DRIVER_SW_VERSION_MIN_NUMBER 15
#define SAL_INFO2_DRIVER_SW_VERSION_MIN_NUMBER 16
#define SAL_INFO2_DRIVER_SW_VERSION_PATCH_NUMBER 0
/**

View file

@ -892,6 +892,7 @@ qat_uclo_get_dev_type(struct icp_qat_fw_loader_handle *handle)
return ICP_QAT_AC_C4XXX_DEV_TYPE;
case ADF_4XXX_PCI_DEVICE_ID:
case ADF_401XX_PCI_DEVICE_ID:
case ADF_402XX_PCI_DEVICE_ID:
return ICP_QAT_AC_4XXX_A_DEV_TYPE;
default:
pr_err("QAT: unsupported device 0x%x\n",

View file

@ -536,8 +536,8 @@ adf_exit_accel_units(struct adf_accel_dev *accel_dev)
}
static const char *
get_obj_name(struct adf_accel_dev *accel_dev,
enum adf_accel_unit_services service)
get_obj_name_4xxx(struct adf_accel_dev *accel_dev,
enum adf_accel_unit_services service)
{
switch (service) {
case ADF_ACCEL_ASYM:
@ -553,6 +553,24 @@ get_obj_name(struct adf_accel_dev *accel_dev,
}
}
static const char *
get_obj_name_402xx(struct adf_accel_dev *accel_dev,
enum adf_accel_unit_services service)
{
switch (service) {
case ADF_ACCEL_ASYM:
return ADF_402XX_ASYM_OBJ;
case ADF_ACCEL_CRYPTO:
return ADF_402XX_SYM_OBJ;
case ADF_ACCEL_COMPRESSION:
return ADF_402XX_DC_OBJ;
case ADF_ACCEL_ADMIN:
return ADF_402XX_ADMIN_OBJ;
default:
return NULL;
}
}
static uint32_t
get_objs_num(struct adf_accel_dev *accel_dev)
{
@ -982,8 +1000,23 @@ adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 id)
hw_data->clock_frequency = ADF_4XXX_AE_FREQ;
hw_data->get_sku = get_sku;
hw_data->heartbeat_ctr_num = ADF_NUM_HB_CNT_PER_AE;
hw_data->fw_name = ADF_4XXX_FW;
hw_data->fw_mmp_name = ADF_4XXX_MMP;
switch (id) {
case ADF_402XX_PCI_DEVICE_ID:
hw_data->fw_name = ADF_402XX_FW;
hw_data->fw_mmp_name = ADF_402XX_MMP;
hw_data->asym_ae_active_thd_mask = DEFAULT_4XXX_ASYM_AE_MASK;
break;
case ADF_401XX_PCI_DEVICE_ID:
hw_data->fw_name = ADF_4XXX_FW;
hw_data->fw_mmp_name = ADF_4XXX_MMP;
hw_data->asym_ae_active_thd_mask = DEFAULT_401XX_ASYM_AE_MASK;
break;
default:
hw_data->fw_name = ADF_4XXX_FW;
hw_data->fw_mmp_name = ADF_4XXX_MMP;
hw_data->asym_ae_active_thd_mask = DEFAULT_4XXX_ASYM_AE_MASK;
}
hw_data->init_admin_comms = adf_init_admin_comms;
hw_data->exit_admin_comms = adf_exit_admin_comms;
hw_data->send_admin_init = adf_4xxx_send_admin_init;
@ -1002,7 +1035,13 @@ adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 id)
hw_data->get_ring_svc_map_data = get_ring_svc_map_data;
hw_data->admin_ae_mask = ADF_4XXX_ADMIN_AE_MASK;
hw_data->get_objs_num = get_objs_num;
hw_data->get_obj_name = get_obj_name;
switch (id) {
case ADF_402XX_PCI_DEVICE_ID:
hw_data->get_obj_name = get_obj_name_402xx;
break;
default:
hw_data->get_obj_name = get_obj_name_4xxx;
}
hw_data->get_obj_cfg_ae_mask = get_obj_cfg_ae_mask;
hw_data->get_service_type = adf_4xxx_get_service_type;
hw_data->set_msix_rttable = set_msix_default_rttable;
@ -1022,15 +1061,6 @@ adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 id)
hw_data->query_storage_cap = 1;
hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;
switch (id) {
case ADF_401XX_PCI_DEVICE_ID:
hw_data->asym_ae_active_thd_mask = DEFAULT_401XX_ASYM_AE_MASK;
break;
case ADF_4XXX_PCI_DEVICE_ID:
default:
hw_data->asym_ae_active_thd_mask = DEFAULT_4XXX_ASYM_AE_MASK;
}
adf_gen4_init_hw_csr_info(&hw_data->csr_info);
adf_gen4_init_pf_pfvf_ops(&hw_data->csr_info.pfvf_ops);
}

View file

@ -87,6 +87,12 @@
#define ADF_4XXX_SYM_OBJ "qat_4xxx_sym.bin"
#define ADF_4XXX_ASYM_OBJ "qat_4xxx_asym.bin"
#define ADF_4XXX_ADMIN_OBJ "qat_4xxx_admin.bin"
#define ADF_402XX_FW "qat_402xx_fw"
#define ADF_402XX_MMP "qat_402xx_mmp_fw"
#define ADF_402XX_DC_OBJ "qat_402xx_dc.bin"
#define ADF_402XX_SYM_OBJ "qat_402xx_sym.bin"
#define ADF_402XX_ASYM_OBJ "qat_402xx_asym.bin"
#define ADF_402XX_ADMIN_OBJ "qat_402xx_admin.bin"
/* Only 3 types of images can be loaded including the admin image */
#define ADF_4XXX_MAX_OBJ 3

View file

@ -22,12 +22,14 @@ static MALLOC_DEFINE(M_QAT_4XXX, "qat_4xxx", "qat_4xxx");
PCI_VENDOR_ID_INTEL, device_id \
}
static const struct pci_device_id adf_pci_tbl[] =
{ ADF_SYSTEM_DEVICE(ADF_4XXX_PCI_DEVICE_ID),
ADF_SYSTEM_DEVICE(ADF_401XX_PCI_DEVICE_ID),
{
0,
} };
static const struct pci_device_id adf_pci_tbl[] = {
ADF_SYSTEM_DEVICE(ADF_4XXX_PCI_DEVICE_ID),
ADF_SYSTEM_DEVICE(ADF_401XX_PCI_DEVICE_ID),
ADF_SYSTEM_DEVICE(ADF_402XX_PCI_DEVICE_ID),
{
0,
}
};
static int
adf_probe(device_t dev)
@ -135,6 +137,7 @@ adf_cleanup_accel(struct adf_accel_dev *accel_dev)
switch (pci_get_device(accel_pci_dev->pci_dev)) {
case ADF_4XXX_PCI_DEVICE_ID:
case ADF_401XX_PCI_DEVICE_ID:
case ADF_402XX_PCI_DEVICE_ID:
adf_clean_hw_data_4xxx(accel_dev->hw_device);
break;
default:

View file

@ -22,12 +22,14 @@ static MALLOC_DEFINE(M_QAT_4XXXVF, "qat_4xxxvf", "qat_4xxxvf");
PCI_VENDOR_ID_INTEL, device_id \
}
static const struct pci_device_id adf_pci_tbl[] =
{ ADF_SYSTEM_DEVICE(ADF_4XXXIOV_PCI_DEVICE_ID),
ADF_SYSTEM_DEVICE(ADF_401XXIOV_PCI_DEVICE_ID),
{
0,
} };
static const struct pci_device_id adf_pci_tbl[] = {
ADF_SYSTEM_DEVICE(ADF_4XXXIOV_PCI_DEVICE_ID),
ADF_SYSTEM_DEVICE(ADF_401XXIOV_PCI_DEVICE_ID),
ADF_SYSTEM_DEVICE(ADF_402XXIOV_PCI_DEVICE_ID),
{
0,
}
};
static int
adf_probe(device_t dev)
@ -76,6 +78,7 @@ adf_cleanup_accel(struct adf_accel_dev *accel_dev)
switch (pci_get_device(accel_pci_dev->pci_dev)) {
case ADF_4XXXIOV_PCI_DEVICE_ID:
case ADF_401XXIOV_PCI_DEVICE_ID:
case ADF_402XXIOV_PCI_DEVICE_ID:
adf_clean_hw_data_4xxxiov(accel_dev->hw_device);
break;
default:

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@ -4,6 +4,9 @@
KMOD= qat_4xxx_fw
FIRMWS= qat_4xxx.bin:qat_4xxx_fw:111 qat_4xxx_mmp.bin:qat_4xxx_mmp_fw:111
FIRMWS= qat_4xxx.bin:qat_4xxx_fw:111 \
qat_4xxx_mmp.bin:qat_4xxx_mmp_fw:111 \
qat_402xx.bin:qat_402xx_fw:111 \
qat_402xx_mmp.bin:qat_402xx_mmp_fw:111
.include <bsd.kmod.mk>