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cxgbe(4): Update shared code and config files
Obtained from: Chelsio Communications MFC after: 1 week Sponsored by: Chelsio Communications
This commit is contained in:
Navdeep Parhar
parent
73a238643a
commit
dda55f83f9
5 changed files with 1399 additions and 456 deletions
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@ -3282,7 +3282,9 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
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0x477d4, 0x477fc,
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0x48000, 0x48004,
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0x48018, 0x4801c,
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0x49304, 0x493f0,
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0x49304, 0x49320,
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0x4932c, 0x4932c,
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0x49334, 0x493f0,
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0x49400, 0x49410,
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0x49460, 0x494f4,
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0x50000, 0x50084,
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@ -3305,7 +3307,9 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
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0x515f0, 0x515f4,
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0x58000, 0x58004,
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0x58018, 0x5801c,
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0x59304, 0x593f0,
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0x59304, 0x59320,
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0x5932c, 0x5932c,
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0x59334, 0x593f0,
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0x59400, 0x59410,
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0x59460, 0x594f4,
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};
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@ -6177,11 +6181,6 @@ static bool mem_intr_handler(struct adapter *adap, int idx, int flags)
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ii.cause_reg = MC_T7_REG(A_MC_P_DDRCTL_INT_CAUSE, i);
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ii.enable_reg = MC_T7_REG(A_MC_P_DDRCTL_INT_ENABLE, i);
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fatal |= t4_handle_intr(adap, &ii, 0, flags);
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snprintf(rname, sizeof(rname), "MC%u_ECC_UE_INT_CAUSE", i);
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ii.cause_reg = MC_T7_REG(A_MC_P_ECC_UE_INT_CAUSE, i);
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ii.enable_reg = MC_T7_REG(A_MC_P_ECC_UE_INT_ENABLE, i);
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fatal |= t4_handle_intr(adap, &ii, 0, flags);
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}
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break;
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}
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File diff suppressed because it is too large
Load diff
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@ -114,7 +114,8 @@
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reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
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reg[0x46004] = 0x3/0x3 #Crypto core reset
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reg[0x46004] = 0x3/0x3 # Crypto core reset
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reg[0x46000] = 0xa/0xe # 16K ESH Hi Extraction window
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#Tick granularities in kbps
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tsch_ticks = 100000, 10000, 1000, 10
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@ -192,14 +193,15 @@
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reg[0x19250] = 0x0/0x3 # Termimate_msg = 0
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# Terminate_with_err = 0
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gc_disable = 3 # 3 - disable gc for hma/mc1 and mc0,
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#Enabling GC for HMA
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gc_disable = 1 # 3 - disable gc for hma/mc1 and mc0,
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# 2 - disable gc for mc1/hma enable mc0,
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# 1 - enable gc for mc1/hma disable mc0,
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# 0 - enable gc for mc1/hma and for mc0,
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# default gc enabled.
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# HMA configuration (uncomment following lines to enable HMA)
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hma_size = 92 # Size (in MBs) of host memory expected
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hma_size = 128 # Size (in MBs) of host memory expected
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hma_regions = iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq # What all regions to place in host memory
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#mc[0]=0
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@ -429,7 +431,7 @@
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nethofld = 1024 # number of user mode ethernet flow contexts
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ncrypto_lookaside = 32
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nclip = 320 # number of clip region entries
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nfilter = 480 # number of filter region entries
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nfilter = 448 # number of filter region entries
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nserver = 480 # number of server region entries
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nhash = 12288 # number of hash region entries
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nhpfilter = 64 # number of high priority filter region entries
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@ -505,12 +507,20 @@
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nfilter = 16 # number of filter region entries
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#nhpfilter = 16 # number of high priority filter region entries
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niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
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nethctrl = 32 # NPORTS*NCPUS
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neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
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nethctrl = 128 # NPORTS*NCPUS
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neq = 256 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
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nserver = 16
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nhash = 1024
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tp_l2t = 512
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protocol = nic_vm, ofld, rddp, rdmac, tlskeys, ipsec_inline, rocev2, nvme_tcp
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tp_ddp = 1
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tp_ddp_iscsi = 1
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tp_tls_key = 1
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tp_stag = 1
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tp_pbl = 3
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tp_rq = 4
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tp_rrq = 2
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tp_srq = 96
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# The following function, 1023, is not an actual PCIE function but is used to
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# configure and reserve firmware internal resources that come from the global
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@ -523,7 +533,7 @@
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cmask = all # access to all channels
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pmask = all # access to all four ports ...
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nexactf = 8 # NPORTS + DCBX +
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nfilter = 16 # number of filter region entries
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nfilter = 48 # number of filter region entries
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#nhpfilter = 0 # number of high priority filter region entries
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@ -594,7 +604,7 @@
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# Bytes)
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#
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[port "0"]
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#dcb = ppp, dcbx, b2b # configure for DCB PPP and enable DCBX offload
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#dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
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hwm = 30
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lwm = 15
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dwm = 30
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@ -604,7 +614,7 @@
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[port "1"]
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#dcb = ppp, dcbx, b2b
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#dcb = ppp, dcbx
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hwm = 30
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lwm = 15
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dwm = 30
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@ -613,7 +623,7 @@
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dcb_app_tlv[2] = 3260, socketnum, 5
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[port "2"]
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#dcb = ppp, dcbx, b2b # configure for DCB PPP and enable DCBX offload
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#dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
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hwm = 30
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lwm = 15
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dwm = 30
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@ -623,7 +633,7 @@
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[port "3"]
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#dcb = ppp, dcbx, b2b
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#dcb = ppp, dcbx
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hwm = 30
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lwm = 15
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dwm = 30
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@ -633,7 +643,7 @@
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[fini]
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version = 0x1425001d
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checksum = 0x684e23fb
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checksum = 0x3671da3b
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# Total resources used by above allocations:
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# Virtual Interfaces: 104
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@ -114,7 +114,8 @@
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reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
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reg[0x46004] = 0x3/0x3 #Crypto core reset
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reg[0x46004] = 0x3/0x3 # Crypto core reset
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reg[0x46000] = 0xa/0xe # 16K ESH Hi Extraction window
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#Tick granularities in kbps
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tsch_ticks = 100000, 10000, 1000, 10
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@ -192,14 +193,15 @@
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reg[0x19250] = 0x0/0x3 # Termimate_msg = 0
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# Terminate_with_err = 0
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gc_disable = 3 # 3 - disable gc for hma/mc1 and mc0,
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#Enabling GC for HMA
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gc_disable = 1 # 3 - disable gc for hma/mc1 and mc0,
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# 2 - disable gc for mc1/hma enable mc0,
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# 1 - enable gc for mc1/hma disable mc0,
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# 0 - enable gc for mc1/hma and for mc0,
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# default gc enabled.
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# HMA configuration (uncomment following lines to enable HMA)
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hma_size = 92 # Size (in MBs) of host memory expected
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hma_size = 128 # Size (in MBs) of host memory expected
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hma_regions = iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq # What all regions to place in host memory
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#mc[0]=0
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@ -429,7 +431,7 @@
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nethofld = 1024 # number of user mode ethernet flow contexts
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ncrypto_lookaside = 32
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nclip = 320 # number of clip region entries
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nfilter = 480 # number of filter region entries
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nfilter = 448 # number of filter region entries
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nserver = 480 # number of server region entries
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nhash = 12288 # number of hash region entries
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nhpfilter = 64 # number of high priority filter region entries
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@ -505,12 +507,20 @@
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nfilter = 16 # number of filter region entries
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#nhpfilter = 16 # number of high priority filter region entries
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niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
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nethctrl = 32 # NPORTS*NCPUS
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neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
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nethctrl = 128 # NPORTS*NCPUS
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neq = 256 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
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nserver = 16
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nhash = 1024
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tp_l2t = 512
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protocol = nic_vm, ofld, rddp, rdmac, tlskeys, ipsec_inline, rocev2, nvme_tcp
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tp_ddp = 1
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tp_ddp_iscsi = 1
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tp_tls_key = 1
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tp_stag = 1
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tp_pbl = 3
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tp_rq = 4
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tp_rrq = 2
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tp_srq = 96
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# The following function, 1023, is not an actual PCIE function but is used to
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# configure and reserve firmware internal resources that come from the global
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@ -523,7 +533,7 @@
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cmask = all # access to all channels
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pmask = all # access to all four ports ...
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nexactf = 8 # NPORTS + DCBX +
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nfilter = 16 # number of filter region entries
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nfilter = 48 # number of filter region entries
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#nhpfilter = 0 # number of high priority filter region entries
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@ -633,7 +643,7 @@
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[fini]
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version = 0x1425001d
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checksum = 0x5cab62d4
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checksum = 0x96513217
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# Total resources used by above allocations:
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# Virtual Interfaces: 104
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@ -1,6 +1,6 @@
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/* This file is automatically generated --- changes will be lost */
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/* Generation Date : Tue Oct 28 05:24:53 PM IST 2025 */
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/* Directory name: t7_sw_reg.txt, Changeset: 5946:0b60ff298e7d */
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/* Generation Date : Thu Dec 11 08:42:53 PM IST 2025 */
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/* Directory name: t7_sw_reg.txt, Changeset: 5950:7c934148528c */
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struct reg_info t7_sge_regs[] = {
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{ "SGE_PF_KDOORBELL", 0x1e000, 0 },
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@ -5785,7 +5785,6 @@ struct reg_info t7_ma_regs[] = {
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{ "CL1_WR_DATA_TO_EN", 1, 1 },
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{ "CL0_WR_DATA_TO_EN", 0, 1 },
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{ "MA_WRITE_TIMEOUT_ERROR_STATUS", 0x78d8, 0 },
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{ "FUTURE_CEXPANSION_WTS", 31, 1 },
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{ "CL14_WR_CMD_TO_ERROR", 30, 1 },
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{ "CL13_WR_CMD_TO_ERROR", 29, 1 },
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{ "CL12_WR_CMD_TO_ERROR", 28, 1 },
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@ -5801,7 +5800,6 @@ struct reg_info t7_ma_regs[] = {
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{ "CL2_WR_CMD_TO_ERROR", 18, 1 },
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{ "CL1_WR_CMD_TO_ERROR", 17, 1 },
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{ "CL0_WR_CMD_TO_ERROR", 16, 1 },
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{ "FUTURE_DEXPANSION_WTS", 15, 1 },
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{ "CL14_WR_DATA_TO_ERROR", 14, 1 },
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{ "CL13_WR_DATA_TO_ERROR", 13, 1 },
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{ "CL12_WR_DATA_TO_ERROR", 12, 1 },
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@ -5818,7 +5816,6 @@ struct reg_info t7_ma_regs[] = {
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{ "CL1_WR_DATA_TO_ERROR", 1, 1 },
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{ "CL0_WR_DATA_TO_ERROR", 0, 1 },
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{ "MA_READ_TIMEOUT_ERROR_ENABLE", 0x78dc, 0 },
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{ "FUTURE_CEXPANSION_RTE", 31, 1 },
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{ "CL14_RD_CMD_TO_EN", 30, 1 },
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{ "CL13_RD_CMD_TO_EN", 29, 1 },
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{ "CL12_RD_CMD_TO_EN", 28, 1 },
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@ -5834,7 +5831,6 @@ struct reg_info t7_ma_regs[] = {
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{ "CL2_RD_CMD_TO_EN", 18, 1 },
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{ "CL1_RD_CMD_TO_EN", 17, 1 },
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{ "CL0_RD_CMD_TO_EN", 16, 1 },
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{ "FUTURE_DEXPANSION_RTE", 15, 1 },
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{ "CL14_RD_DATA_TO_EN", 14, 1 },
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{ "CL13_RD_DATA_TO_EN", 13, 1 },
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{ "CL12_RD_DATA_TO_EN", 12, 1 },
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@ -5851,7 +5847,6 @@ struct reg_info t7_ma_regs[] = {
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{ "CL1_RD_DATA_TO_EN", 1, 1 },
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{ "CL0_RD_DATA_TO_EN", 0, 1 },
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{ "MA_READ_TIMEOUT_ERROR_STATUS", 0x78e0, 0 },
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{ "FUTURE_CEXPANSION_RTS", 31, 1 },
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{ "CL14_RD_CMD_TO_ERROR", 30, 1 },
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{ "CL13_RD_CMD_TO_ERROR", 29, 1 },
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{ "CL12_RD_CMD_TO_ERROR", 28, 1 },
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@ -5867,7 +5862,7 @@ struct reg_info t7_ma_regs[] = {
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{ "CL2_RD_CMD_TO_ERROR", 18, 1 },
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{ "CL1_RD_CMD_TO_ERROR", 17, 1 },
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{ "CL0_RD_CMD_TO_ERROR", 16, 1 },
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{ "FUTURE_DEXPANSION_RTS", 14, 2 },
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{ "CL14_RD_DATA_TO_ERROR", 14, 1 },
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{ "CL13_RD_DATA_TO_ERROR", 13, 1 },
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{ "CL12_RD_DATA_TO_ERROR", 12, 1 },
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{ "CL11_RD_DATA_TO_ERROR", 11, 1 },
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@ -5892,7 +5887,7 @@ struct reg_info t7_ma_regs[] = {
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{ "RD_WIN", 8, 8 },
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{ "WR_WIN", 0, 8 },
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{ "MA_IF_PARITY_ERROR_ENABLE", 0x78f0, 0 },
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{ "FUTURE_DEXPANSION_IPE", 14, 18 },
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{ "CL14_IF_PAR_EN", 14, 1 },
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{ "CL13_IF_PAR_EN", 13, 1 },
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{ "CL12_IF_PAR_EN", 12, 1 },
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{ "CL11_IF_PAR_EN", 11, 1 },
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@ -5908,7 +5903,7 @@ struct reg_info t7_ma_regs[] = {
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{ "CL1_IF_PAR_EN", 1, 1 },
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{ "CL0_IF_PAR_EN", 0, 1 },
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{ "MA_IF_PARITY_ERROR_STATUS", 0x78f4, 0 },
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{ "FUTURE_DEXPANSION_IPS", 14, 18 },
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{ "CL14_IF_PAR_ERROR", 14, 1 },
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{ "CL13_IF_PAR_ERROR", 13, 1 },
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{ "CL12_IF_PAR_ERROR", 12, 1 },
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{ "CL11_IF_PAR_ERROR", 11, 1 },
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@ -9192,170 +9187,470 @@ struct reg_info t7_mps_regs[] = {
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{ "MPS_RX_PORT_GAP", 0x1106c, 0 },
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{ "MPS_CTL_STAT", 0x11070, 0 },
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{ "MPS_RX_PERR_INT_CAUSE", 0x11074, 0 },
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{ "MAC_IN_FIFO_768b", 30, 1 },
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{ "INT_ERR_INT", 29, 1 },
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{ "INT_ERR_INT", 30, 1 },
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{ "FLOP_PERR", 28, 1 },
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{ "ATRB", 18, 1 },
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{ "RPLC_MAP", 13, 5 },
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{ "TKN_RUNT_DROP_FIFO", 12, 1 },
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{ "PPM3", 9, 3 },
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{ "PPM2", 6, 3 },
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{ "PPM1", 3, 3 },
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{ "PPM0", 0, 3 },
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{ "mps_rx_atrb_map_perr", 23, 1 },
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{ "RPLC_MAP_vni_perr", 18, 5 },
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{ "RPLC_MAP_mcast_perr", 13, 5 },
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{ "PPM3_perr", 9, 3 },
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{ "PPM2_perr", 6, 3 },
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{ "PPM1_perr", 3, 3 },
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{ "PPM0_perr", 0, 3 },
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{ "MPS_RX_PERR_INT_ENABLE", 0x11078, 0 },
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{ "INT_ERR_INT", 30, 1 },
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{ "FLOP_PERR", 28, 1 },
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{ "ATRB", 18, 1 },
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{ "RPLC_MAP", 13, 5 },
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{ "PPM3", 9, 3 },
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{ "PPM2", 6, 3 },
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{ "PPM1", 3, 3 },
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{ "PPM0", 0, 3 },
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{ "mps_rx_atrb_map_perr", 23, 1 },
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{ "RPLC_MAP_vni_perr", 18, 5 },
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{ "RPLC_MAP_mcast_perr", 13, 5 },
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{ "PPM3_perr", 9, 3 },
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{ "PPM2_perr", 6, 3 },
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{ "PPM1_perr", 3, 3 },
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{ "PPM0_perr", 0, 3 },
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{ "MPS_RX_PERR_ENABLE", 0x1107c, 0 },
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{ "INT_ERR_INT", 30, 1 },
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{ "FLOP_PERR", 28, 1 },
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{ "ATRB", 18, 1 },
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{ "RPLC_MAP", 13, 5 },
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{ "PPM3", 9, 3 },
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{ "PPM2", 6, 3 },
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{ "PPM1", 3, 3 },
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{ "PPM0", 0, 3 },
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{ "mps_rx_atrb_ma_perrp", 23, 1 },
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{ "RPLC_MAP_vn_perri", 18, 5 },
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{ "RPLC_MAP_mcast_perr", 13, 5 },
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{ "PPM3_perr", 9, 3 },
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{ "PPM2_perr", 6, 3 },
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{ "PPM1_perr", 3, 3 },
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{ "PPM0_perr", 0, 3 },
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{ "MPS_RX_PERR_INT_CAUSE2", 0x1108c, 0 },
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{ "crypt2mps_rx_intf_fifo", 28, 4 },
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{ "inic2mps_tx0_perr", 27, 1 },
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{ "inic2mps_tx1_perr", 26, 1 },
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{ "xgmac2mps_rx0_perr", 25, 1 },
|
||||
{ "xgmac2mps_rx1_perr", 24, 1 },
|
||||
{ "mps2crypto_rx_intf_fifo", 20, 4 },
|
||||
{ "mac_rx_pproc_mps2tp_tf", 19, 1 },
|
||||
{ "mac_rx_pproc_lb_ch3", 18, 1 },
|
||||
{ "mac_rx_pproc_lb_ch2", 17, 1 },
|
||||
{ "mac_rx_pproc_lb_ch1", 16, 1 },
|
||||
{ "mac_rx_pproc_lb_ch0", 15, 1 },
|
||||
{ "mac_rx_pproc_dwrr_ch0_3", 14, 1 },
|
||||
{ "mac_rx_fifo_perr", 13, 1 },
|
||||
{ "crypto2mps_rx0_perr", 31, 1 },
|
||||
{ "crypto2mps_rx1_perr", 30, 1 },
|
||||
{ "crypto2mps_rx2_perr", 29, 1 },
|
||||
{ "crypto2mps_rx3_perr", 28, 1 },
|
||||
{ "inic2mps_tx1_perr", 27, 1 },
|
||||
{ "inic2mps_tx0_perr", 26, 1 },
|
||||
{ "xgmac2mps_rx1_perr", 25, 1 },
|
||||
{ "xgmac2mps_rx0_perr", 24, 1 },
|
||||
{ "mps2crypto_ch0_intf_fifo_perr", 20, 4 },
|
||||
{ "rx_final_tf_fifo_perr", 19, 1 },
|
||||
{ "mps_lb_fifo_perr", 15, 4 },
|
||||
{ "mps_dwrr_fifo_perr", 14, 1 },
|
||||
{ "MAC_tf_fifo_perr", 13, 1 },
|
||||
{ "mac2mps_pt3_perr", 12, 1 },
|
||||
{ "mac2mps_pt2_perr", 11, 1 },
|
||||
{ "mac2mps_pt1_perr", 10, 1 },
|
||||
{ "mac2mps_pt0_perr", 9, 1 },
|
||||
{ "lpbk_fifo_perr", 8, 1 },
|
||||
{ "tp2mps_tf_fifo_perr", 7, 1 },
|
||||
{ "tp_lpbk_fifo_perr", 8, 1 },
|
||||
{ "tp_lpbk_tf_perr", 7, 1 },
|
||||
{ "RSDV1", 0, 7 },
|
||||
{ "MPS_RX_PERR_INT_ENABLE2", 0x11090, 0 },
|
||||
{ "crypt2mps_rx_intf_fifo", 28, 4 },
|
||||
{ "inic2mps_tx0_perr", 27, 1 },
|
||||
{ "inic2mps_tx1_perr", 26, 1 },
|
||||
{ "xgmac2mps_rx0_perr", 25, 1 },
|
||||
{ "xgmac2mps_rx1_perr", 24, 1 },
|
||||
{ "mps2crypto_rx_intf_fifo", 20, 4 },
|
||||
{ "mac_rx_pproc_mps2tp_tf", 19, 1 },
|
||||
{ "mac_rx_pproc_lb_ch3", 18, 1 },
|
||||
{ "mac_rx_pproc_lb_ch2", 17, 1 },
|
||||
{ "mac_rx_pproc_lb_ch1", 16, 1 },
|
||||
{ "mac_rx_pproc_lb_ch0", 15, 1 },
|
||||
{ "mac_rx_pproc_dwrr_ch0_3", 14, 1 },
|
||||
{ "mac_rx_fifo_perr", 13, 1 },
|
||||
{ "crypto2mps_rx0_perr", 31, 1 },
|
||||
{ "crypto2mps_rx1_perr", 30, 1 },
|
||||
{ "crypto2mps_rx2_perr", 29, 1 },
|
||||
{ "crypto2mps_rx3_perr", 28, 1 },
|
||||
{ "inic2mps_tx1_perr", 27, 1 },
|
||||
{ "inic2mps_tx0_perr", 26, 1 },
|
||||
{ "xgmac2mps_rx1_perr", 25, 1 },
|
||||
{ "xgmac2mps_rx0_perr", 24, 1 },
|
||||
{ "mps2crypto_ch0_intf_fifo_perr", 20, 4 },
|
||||
{ "rx_final_tf_fifo_perr", 19, 1 },
|
||||
{ "mps_lb_fifo_perr", 15, 4 },
|
||||
{ "mps_dwrr_fifo_perr", 14, 1 },
|
||||
{ "MAC_tf_fifo_perr", 13, 1 },
|
||||
{ "mac2mps_pt3_perr", 12, 1 },
|
||||
{ "mac2mps_pt2_perr", 11, 1 },
|
||||
{ "mac2mps_pt1_perr", 10, 1 },
|
||||
{ "mac2mps_pt0_perr", 9, 1 },
|
||||
{ "lpbk_fifo_perr", 8, 1 },
|
||||
{ "tp2mps_tf_fifo_perr", 7, 1 },
|
||||
{ "tp_lpbk_fifo_perr", 8, 1 },
|
||||
{ "tp_lpbk_tf_perr", 7, 1 },
|
||||
{ "RSDV1", 0, 7 },
|
||||
{ "MPS_RX_PERR_ENABLE2", 0x11094, 0 },
|
||||
{ "crypt2mps_rx_intf_fifo", 28, 4 },
|
||||
{ "inic2mps_tx0_perr", 27, 1 },
|
||||
{ "inic2mps_tx1_perr", 26, 1 },
|
||||
{ "xgmac2mps_rx0_perr", 25, 1 },
|
||||
{ "xgmac2mps_rx1_perr", 24, 1 },
|
||||
{ "mps2crypto_rx_intf_fifo", 20, 4 },
|
||||
{ "mac_rx_pproc_mps2tp_tf", 19, 1 },
|
||||
{ "mac_rx_pproc_lb_ch3", 18, 1 },
|
||||
{ "mac_rx_pproc_lb_ch2", 17, 1 },
|
||||
{ "mac_rx_pproc_lb_ch1", 16, 1 },
|
||||
{ "mac_rx_pproc_lb_ch0", 15, 1 },
|
||||
{ "mac_rx_pproc_dwrr_ch0_3", 14, 1 },
|
||||
{ "mac_rx_fifo_perr", 13, 1 },
|
||||
{ "crypto2mps_rx0_perr", 31, 1 },
|
||||
{ "crypto2mps_rx1_perr", 30, 1 },
|
||||
{ "crypto2mps_rx2_perr", 29, 1 },
|
||||
{ "crypto2mps_rx3_perr", 28, 1 },
|
||||
{ "inic2mps_tx1_perr", 27, 1 },
|
||||
{ "inic2mps_tx0_perr", 26, 1 },
|
||||
{ "xgmac2mps_rx1_perr", 25, 1 },
|
||||
{ "xgmac2mps_rx0_perr", 24, 1 },
|
||||
{ "mps2crypto_ch0_intf_fifo_perr", 20, 4 },
|
||||
{ "rx_final_tf_fifo_perr", 19, 1 },
|
||||
{ "mps_lb_fifo_perr", 15, 4 },
|
||||
{ "mps_dwrr_fifo_perr", 14, 1 },
|
||||
{ "MAC_tf_fifo_perr", 13, 1 },
|
||||
{ "mac2mps_pt3_perr", 12, 1 },
|
||||
{ "mac2mps_pt2_perr", 11, 1 },
|
||||
{ "mac2mps_pt1_perr", 10, 1 },
|
||||
{ "mac2mps_pt0_perr", 9, 1 },
|
||||
{ "lpbk_fifo_perr", 8, 1 },
|
||||
{ "tp2mps_tf_fifo_perr", 7, 1 },
|
||||
{ "tp_lpbk_fifo_perr", 8, 1 },
|
||||
{ "tp_lpbk_tf_perr", 7, 1 },
|
||||
{ "RSDV1", 0, 7 },
|
||||
{ "MPS_RX_PERR_INT_CAUSE3", 0x11310, 0 },
|
||||
{ "fifo_repl_ch3_cerr", 28, 1 },
|
||||
{ "fifo_repl_ch2_cerr", 27, 1 },
|
||||
{ "fifo_repl_ch1_cerr", 26, 1 },
|
||||
{ "fifo_repl_ch0_cerr", 25, 1 },
|
||||
{ "vlan_filter_ram_cerr", 24, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch3", 23, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch3", 22, 1 },
|
||||
{ "id_fifo_in_perr_ch3", 21, 1 },
|
||||
{ "desc_hdr2_perr_ch3", 20, 1 },
|
||||
{ "fifo_repl_perr_ch3", 19, 1 },
|
||||
{ "mps_rx_td_perr_ch3", 18, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch2", 17, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch2", 16, 1 },
|
||||
{ "id_fifo_in_perr_ch2", 15, 1 },
|
||||
{ "desc_hdr2_perr_ch2", 14, 1 },
|
||||
{ "fifo_repl_perr_ch2", 13, 1 },
|
||||
{ "mps_rx_td_perr_ch2", 12, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch1", 11, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch1", 10, 1 },
|
||||
{ "id_fifo_in_perr_ch1", 9, 1 },
|
||||
{ "desc_hdr2_perr_ch1", 8, 1 },
|
||||
{ "fifo_repl_perr_ch1", 7, 1 },
|
||||
{ "mps_rx_td_perr_ch1", 6, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch0", 5, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch0", 4, 1 },
|
||||
{ "id_fifo_in_perr_ch0", 3, 1 },
|
||||
{ "desc_hdr2_perr_ch0", 2, 1 },
|
||||
{ "fifo_repl_perr_ch0", 1, 1 },
|
||||
{ "mps_rx_td_perr_ch0", 0, 1 },
|
||||
{ "MPS_RX_PERR_INT_ENABLE3", 0x11314, 0 },
|
||||
{ "fifo_repl_ch3_cerr", 28, 1 },
|
||||
{ "fifo_repl_ch2_cerr", 27, 1 },
|
||||
{ "fifo_repl_ch1_cerr", 26, 1 },
|
||||
{ "fifo_repl_ch0_cerr", 25, 1 },
|
||||
{ "vlan_filter_ram_cerr", 24, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch3", 23, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch3", 22, 1 },
|
||||
{ "id_fifo_in_perr_ch3", 21, 1 },
|
||||
{ "desc_hdr2_perr_ch3", 20, 1 },
|
||||
{ "fifo_repl_perr_ch3", 19, 1 },
|
||||
{ "mps_rx_td_perr_ch3", 18, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch2", 17, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch2", 16, 1 },
|
||||
{ "id_fifo_in_perr_ch2", 15, 1 },
|
||||
{ "desc_hdr2_perr_ch2", 14, 1 },
|
||||
{ "fifo_repl_perr_ch2", 13, 1 },
|
||||
{ "mps_rx_td_perr_ch2", 12, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch1", 11, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch1", 10, 1 },
|
||||
{ "id_fifo_in_perr_ch1", 9, 1 },
|
||||
{ "desc_hdr2_perr_ch1", 8, 1 },
|
||||
{ "fifo_repl_perr_ch1", 7, 1 },
|
||||
{ "mps_rx_td_perr_ch1", 6, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch0", 5, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch0", 4, 1 },
|
||||
{ "id_fifo_in_perr_ch0", 3, 1 },
|
||||
{ "desc_hdr2_perr_ch0", 2, 1 },
|
||||
{ "fifo_repl_perr_ch0", 1, 1 },
|
||||
{ "mps_rx_td_perr_ch0", 0, 1 },
|
||||
{ "MPS_RX_PERR_ENABLE3", 0x11318, 0 },
|
||||
{ "fifo_repl_ch3_cerr", 28, 1 },
|
||||
{ "fifo_repl_ch2_cerr", 27, 1 },
|
||||
{ "fifo_repl_ch1_cerr", 26, 1 },
|
||||
{ "fifo_repl_ch0_cerr", 25, 1 },
|
||||
{ "vlan_filter_ram_cerr", 24, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch3", 23, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch3", 22, 1 },
|
||||
{ "id_fifo_in_perr_ch3", 21, 1 },
|
||||
{ "desc_hdr2_perr_ch3", 20, 1 },
|
||||
{ "fifo_repl_perr_ch3", 19, 1 },
|
||||
{ "mps_rx_td_perr_ch3", 18, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch2", 17, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch2", 16, 1 },
|
||||
{ "id_fifo_in_perr_ch2", 15, 1 },
|
||||
{ "desc_hdr2_perr_ch2", 14, 1 },
|
||||
{ "fifo_repl_perr_ch2", 13, 1 },
|
||||
{ "mps_rx_td_perr_ch2", 12, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch1", 11, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch1", 10, 1 },
|
||||
{ "id_fifo_in_perr_ch1", 9, 1 },
|
||||
{ "desc_hdr2_perr_ch1", 8, 1 },
|
||||
{ "fifo_repl_perr_ch1", 7, 1 },
|
||||
{ "mps_rx_td_perr_ch1", 6, 1 },
|
||||
{ "mps_rx_td_stat_fifo_perr_ch0", 5, 1 },
|
||||
{ "rplct_hdr_fifo_in_perr_ch0", 4, 1 },
|
||||
{ "id_fifo_in_perr_ch0", 3, 1 },
|
||||
{ "desc_hdr2_perr_ch0", 2, 1 },
|
||||
{ "fifo_repl_perr_ch0", 1, 1 },
|
||||
{ "mps_rx_td_perr_ch0", 0, 1 },
|
||||
{ "MPS_RX_PERR_INT_CAUSE4", 0x1131c, 0 },
|
||||
{ "CLS", 20, 6 },
|
||||
{ "rx_pre_proc", 16, 4 },
|
||||
{ "pproc3", 12, 4 },
|
||||
{ "pproc2", 8, 4 },
|
||||
{ "pproc1", 4, 4 },
|
||||
{ "pproc0", 0, 4 },
|
||||
{ "vni_multicast_fifo_ecc_err_ch3", 30, 1 },
|
||||
{ "vni_multicast_fifo_ecc_err_ch2", 29, 1 },
|
||||
{ "hash_sram_cls_eng1", 28, 1 },
|
||||
{ "hash_sram_cls_eng0", 27, 1 },
|
||||
{ "cls_tcam_sram_cls_eng1", 26, 1 },
|
||||
{ "cls_tcam_crc_sram_cls_eng1", 25, 1 },
|
||||
{ "cls_tcam_sram_cls_eng0", 24, 1 },
|
||||
{ "cls_tcam_crc_sram_cls_eng0", 23, 1 },
|
||||
{ "lb_fifo_ecc_err", 19, 4 },
|
||||
{ "dwrr_ch_fifo_ecc_err", 18, 1 },
|
||||
{ "mac_rx_fifo_ecc_err", 17, 1 },
|
||||
{ "lpbk_rx_fifo_ecc_err", 16, 1 },
|
||||
{ "crs_data_store_n_fwd_ch3", 15, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch3", 14, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch3", 13, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch3", 12, 1 },
|
||||
{ "crs_data_store_n_fwd_ch2", 11, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch2", 10, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch2", 9, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch2", 8, 1 },
|
||||
{ "crs_data_store_n_fwd_ch1", 7, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch1", 6, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch1", 5, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch1", 4, 1 },
|
||||
{ "crs_data_store_n_fwd_ch0", 3, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch0", 2, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch0", 1, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch0", 0, 1 },
|
||||
{ "MPS_RX_PERR_INT_ENABLE4", 0x11320, 0 },
|
||||
{ "CLS", 20, 6 },
|
||||
{ "rx_pre_proc", 16, 4 },
|
||||
{ "pproc3", 12, 4 },
|
||||
{ "pproc2", 8, 4 },
|
||||
{ "pproc1", 4, 4 },
|
||||
{ "pproc0", 0, 4 },
|
||||
{ "vni_multicast_fifo_ecc_err_ch3", 30, 1 },
|
||||
{ "vni_multicast_fifo_ecc_err_ch2", 29, 1 },
|
||||
{ "hash_sram_cls_eng1", 28, 1 },
|
||||
{ "hash_sram_cls_eng0", 27, 1 },
|
||||
{ "cls_tcam_sram_cls_eng1", 26, 1 },
|
||||
{ "cls_tcam_crc_sram_cls_eng1", 25, 1 },
|
||||
{ "cls_tcam_sram_cls_eng0", 24, 1 },
|
||||
{ "cls_tcam_crc_sram_cls_eng0", 23, 1 },
|
||||
{ "lb_fifo_ecc_err", 19, 4 },
|
||||
{ "dwrr_ch_fifo_ecc_err", 18, 1 },
|
||||
{ "mac_rx_fifo_ecc_err", 17, 1 },
|
||||
{ "lpbk_rx_fifo_ecc_err", 16, 1 },
|
||||
{ "crs_data_store_n_fwd_ch3", 15, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch3", 14, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch3", 13, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch3", 12, 1 },
|
||||
{ "crs_data_store_n_fwd_ch2", 11, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch2", 10, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch2", 9, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch2", 8, 1 },
|
||||
{ "crs_data_store_n_fwd_ch1", 7, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch1", 6, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch1", 5, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch1", 4, 1 },
|
||||
{ "crs_data_store_n_fwd_ch0", 3, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch0", 2, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch0", 1, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch0", 0, 1 },
|
||||
{ "MPS_RX_PERR_ENABLE4", 0x11324, 0 },
|
||||
{ "CLS", 20, 6 },
|
||||
{ "rx_pre_proc", 16, 4 },
|
||||
{ "pproc3", 12, 4 },
|
||||
{ "pproc2", 8, 4 },
|
||||
{ "pproc1", 4, 4 },
|
||||
{ "pproc0", 0, 4 },
|
||||
{ "vni_multicast_fifo_ecc_err_ch3", 30, 1 },
|
||||
{ "vni_multicast_fifo_ecc_err_ch2", 29, 1 },
|
||||
{ "hash_sram_cls_eng1", 28, 1 },
|
||||
{ "hash_sram_cls_eng0", 27, 1 },
|
||||
{ "cls_tcam_sram_cls_eng1", 26, 1 },
|
||||
{ "cls_tcam_crc_sram_cls_eng1", 25, 1 },
|
||||
{ "cls_tcam_sram_cls_eng0", 24, 1 },
|
||||
{ "cls_tcam_crc_sram_cls_eng0", 23, 1 },
|
||||
{ "lb_fifo_ecc_err", 19, 4 },
|
||||
{ "dwrr_ch_fifo_ecc_err", 18, 1 },
|
||||
{ "mac_rx_fifo_ecc_err", 17, 1 },
|
||||
{ "lpbk_rx_fifo_ecc_err", 16, 1 },
|
||||
{ "crs_data_store_n_fwd_ch3", 15, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch3", 14, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch3", 13, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch3", 12, 1 },
|
||||
{ "crs_data_store_n_fwd_ch2", 11, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch2", 10, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch2", 9, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch2", 8, 1 },
|
||||
{ "crs_data_store_n_fwd_ch1", 7, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch1", 6, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch1", 5, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch1", 4, 1 },
|
||||
{ "crs_data_store_n_fwd_ch0", 3, 1 },
|
||||
{ "trace_fwd_fifo_cerr_ch0", 2, 1 },
|
||||
{ "transparent_encap_fwd_fifo_cerr_ch0", 1, 1 },
|
||||
{ "PTP_trace_fwd_fifo_cerr_ch0", 0, 1 },
|
||||
{ "MPS_RX_PERR_INT_CAUSE5", 0x11328, 0 },
|
||||
{ "mps2cryp_rx_fifo", 26, 4 },
|
||||
{ "rx_out", 20, 6 },
|
||||
{ "MEM_WRAP", 0, 20 },
|
||||
{ "mps2cryp_rx_fifo3_perr", 31, 1 },
|
||||
{ "mps2cryp_rx_fifo2_perr", 30, 1 },
|
||||
{ "mps2cryp_rx_fifo1_perr", 29, 1 },
|
||||
{ "mps2cryp_rx_fifo0_perr", 28, 1 },
|
||||
{ "vni_multicast_sram2_perr", 27, 1 },
|
||||
{ "vni_multicast_sram1_perr", 26, 1 },
|
||||
{ "vni_multicast_sram0_perr", 25, 1 },
|
||||
{ "mac_multicast_sram4_perr", 24, 1 },
|
||||
{ "mac_multicast_sram3_perr", 23, 1 },
|
||||
{ "mac_multicast_sram2_perr", 22, 1 },
|
||||
{ "mac_multicast_sram1_perr", 21, 1 },
|
||||
{ "mac_multicast_sram0_perr", 20, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 19, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 18, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 17, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 16, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
|
||||
{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
|
||||
{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
|
||||
{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
|
||||
{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
|
||||
{ "MPS_RX_PERR_INT_ENABLE5", 0x1132c, 0 },
|
||||
{ "mps2cryp_rx_fifo", 26, 4 },
|
||||
{ "rx_out", 20, 6 },
|
||||
{ "MEM_WRAP", 0, 20 },
|
||||
{ "mps2cryp_rx_fifo3_perr", 31, 1 },
|
||||
{ "mps2cryp_rx_fifo2_perr", 30, 1 },
|
||||
{ "mps2cryp_rx_fifo1_perr", 29, 1 },
|
||||
{ "mps2cryp_rx_fifo0_perr", 28, 1 },
|
||||
{ "vni_multicast_sram2_perr", 27, 1 },
|
||||
{ "vni_multicast_sram1_perr", 26, 1 },
|
||||
{ "vni_multicast_sram0_perr", 25, 1 },
|
||||
{ "mac_multicast_sram4_perr", 24, 1 },
|
||||
{ "mac_multicast_sram3_perr", 23, 1 },
|
||||
{ "mac_multicast_sram2_perr", 22, 1 },
|
||||
{ "mac_multicast_sram1_perr", 21, 1 },
|
||||
{ "mac_multicast_sram0_perr", 20, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 19, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 18, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 17, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 16, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
|
||||
{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
|
||||
{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
|
||||
{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
|
||||
{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
|
||||
{ "MPS_RX_PERR_ENABLE5", 0x11330, 0 },
|
||||
{ "mps2cryp_rx_fifo", 26, 4 },
|
||||
{ "rx_out", 20, 6 },
|
||||
{ "MEM_WRAP", 0, 20 },
|
||||
{ "mps2cryp_rx_fifo3_perr", 31, 1 },
|
||||
{ "mps2cryp_rx_fifo2_perr", 30, 1 },
|
||||
{ "mps2cryp_rx_fifo1_perr", 29, 1 },
|
||||
{ "mps2cryp_rx_fifo0_perr", 28, 1 },
|
||||
{ "vni_multicast_sram2_perr", 27, 1 },
|
||||
{ "vni_multicast_sram1_perr", 26, 1 },
|
||||
{ "vni_multicast_sram0_perr", 25, 1 },
|
||||
{ "mac_multicast_sram4_perr", 24, 1 },
|
||||
{ "mac_multicast_sram3_perr", 23, 1 },
|
||||
{ "mac_multicast_sram2_perr", 22, 1 },
|
||||
{ "mac_multicast_sram1_perr", 21, 1 },
|
||||
{ "mac_multicast_sram0_perr", 20, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 19, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 18, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 17, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 16, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
|
||||
{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
|
||||
{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
|
||||
{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
|
||||
{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
|
||||
{ "MPS_RX_PERR_INJECT", 0x11080, 0 },
|
||||
{ "MemSel", 1, 5 },
|
||||
{ "InjectDataErr", 0, 1 },
|
||||
{ "MPS_RX_PERR_INT_CAUSE6", 0x11334, 0 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 23, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 22, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 21, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 20, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo3_perr", 19, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo2_perr", 18, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo1_perr", 17, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo0_perr", 16, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
|
||||
{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
|
||||
{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
|
||||
{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
|
||||
{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
|
||||
{ "MPS_RX_PERR_INT_ENABLE6", 0x11338, 0 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 23, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 22, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 21, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 20, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo3_perr", 19, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo2_perr", 18, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo1_perr", 17, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo0_perr", 16, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
|
||||
{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
|
||||
{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
|
||||
{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
|
||||
{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
|
||||
{ "MPS_RX_PERR_ENABLE6", 0x1133c, 0 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 23, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 22, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 21, 1 },
|
||||
{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 20, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo3_perr", 19, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo2_perr", 18, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo1_perr", 17, 1 },
|
||||
{ "mem_wrap_cr2mps_updtd_hdr_fifo0_perr", 16, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
|
||||
{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
|
||||
{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
|
||||
{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
|
||||
{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
|
||||
{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
|
||||
{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
|
||||
{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
|
||||
{ "MPS_RX_FUNC_INT_CAUSE", 0x11084, 0 },
|
||||
{ "MTU_ERR_INT3", 19, 1 },
|
||||
{ "MTU_ERR_INT2", 18, 1 },
|
||||
{ "MTU_ERR_INT1", 17, 1 },
|
||||
{ "MTU_ERR_INT0", 16, 1 },
|
||||
{ "SE_CNT_ERR_INT", 15, 1 },
|
||||
{ "FRM_ERR_INT", 14, 1 },
|
||||
{ "LEN_ERR_INT", 13, 1 },
|
||||
{ "INT_ERR_INT", 8, 5 },
|
||||
{ "PG_TH_INT7", 7, 1 },
|
||||
{ "PG_TH_INT6", 6, 1 },
|
||||
{ "PG_TH_INT5", 5, 1 },
|
||||
{ "PG_TH_INT4", 4, 1 },
|
||||
{ "PG_TH_INT3", 3, 1 },
|
||||
{ "PG_TH_INT2", 2, 1 },
|
||||
{ "PG_TH_INT1", 1, 1 },
|
||||
{ "PG_TH_INT0", 0, 1 },
|
||||
{ "mtu_err3", 19, 1 },
|
||||
{ "mtu_err2", 18, 1 },
|
||||
{ "mtu_err1", 17, 1 },
|
||||
{ "mtu_err0", 16, 1 },
|
||||
{ "dbg_len_err", 15, 1 },
|
||||
{ "dbg_spi_err", 14, 1 },
|
||||
{ "dbg_se_cnt_err", 13, 1 },
|
||||
{ "dbg_spi_len_se_cnt_err", 12, 1 },
|
||||
{ "MPS_RX_FUNC_INT_ENABLE", 0x11088, 0 },
|
||||
{ "MTU_ERR_INT3", 19, 1 },
|
||||
{ "MTU_ERR_INT2", 18, 1 },
|
||||
{ "MTU_ERR_INT1", 17, 1 },
|
||||
{ "MTU_ERR_INT0", 16, 1 },
|
||||
{ "SE_CNT_ERR_INT", 15, 1 },
|
||||
{ "FRM_ERR_INT", 14, 1 },
|
||||
{ "LEN_ERR_INT", 13, 1 },
|
||||
{ "INT_ERR_INT", 8, 5 },
|
||||
{ "PG_TH_INT7", 7, 1 },
|
||||
{ "PG_TH_INT6", 6, 1 },
|
||||
{ "PG_TH_INT5", 5, 1 },
|
||||
{ "PG_TH_INT4", 4, 1 },
|
||||
{ "PG_TH_INT3", 3, 1 },
|
||||
{ "PG_TH_INT2", 2, 1 },
|
||||
{ "PG_TH_INT1", 1, 1 },
|
||||
{ "PG_TH_INT0", 0, 1 },
|
||||
{ "mtu_err3", 19, 1 },
|
||||
{ "mtu_err2", 18, 1 },
|
||||
{ "mtu_err1", 17, 1 },
|
||||
{ "mtu_err0", 16, 1 },
|
||||
{ "dbg_len_err", 15, 1 },
|
||||
{ "dbg_spi_err", 14, 1 },
|
||||
{ "dbg_se_cnt_err", 13, 1 },
|
||||
{ "dbg_spi_len_se_cnt_err", 12, 1 },
|
||||
{ "MPS_RX_REPL_CTL", 0x11098, 0 },
|
||||
{ "MPS_RX_PPP_ATRB", 0x1109c, 0 },
|
||||
{ "ETYPE", 16, 16 },
|
||||
|
|
@ -10512,23 +10807,45 @@ struct reg_info t7_mps_regs[] = {
|
|||
{ "FRMERR", 27, 1 },
|
||||
{ "SECNTERR", 26, 1 },
|
||||
{ "BUBBLE", 25, 1 },
|
||||
{ "TxTokenFifo", 15, 10 },
|
||||
{ "PERR_TP2MPS_TFIFO", 13, 2 },
|
||||
{ "TxDescFifo", 9, 4 },
|
||||
{ "TxDataFifo", 5, 4 },
|
||||
{ "Ncsi", 4, 1 },
|
||||
{ "TP", 0, 4 },
|
||||
{ "tx_tf_fifo_perr", 19, 1 },
|
||||
{ "tx_fifo_perr", 18, 1 },
|
||||
{ "non_ipsec_tx_fifo3_perr", 17, 1 },
|
||||
{ "non_ipsec_tx_fifo2_perr", 16, 1 },
|
||||
{ "non_ipsec_tx_fifo1_perr", 15, 1 },
|
||||
{ "non_ipsec_tx_fifo0_perr", 14, 1 },
|
||||
{ "tp2mps_tx0", 13, 1 },
|
||||
{ "crypto2mps_tx0", 12, 1 },
|
||||
{ "tp2mps_tx1", 11, 1 },
|
||||
{ "crypto2mps_tx1", 10, 1 },
|
||||
{ "tp2mps_tx2", 9, 1 },
|
||||
{ "crypto2mps_tx2", 8, 1 },
|
||||
{ "tp2mps_tx3", 7, 1 },
|
||||
{ "crypto2mps_tx3", 6, 1 },
|
||||
{ "ncsi2mps", 5, 1 },
|
||||
{ "Ncsi_perr", 4, 1 },
|
||||
{ "TP_perr", 0, 4 },
|
||||
{ "MPS_TX_INT_CAUSE", 0x9408, 0 },
|
||||
{ "PortErr", 28, 1 },
|
||||
{ "FRMERR", 27, 1 },
|
||||
{ "SECNTERR", 26, 1 },
|
||||
{ "BUBBLE", 25, 1 },
|
||||
{ "TxTokenFifo", 15, 10 },
|
||||
{ "PERR_TP2MPS_TFIFO", 13, 2 },
|
||||
{ "TxDescFifo", 9, 4 },
|
||||
{ "TxDataFifo", 5, 4 },
|
||||
{ "Ncsi", 4, 1 },
|
||||
{ "TP", 0, 4 },
|
||||
{ "tx_tf_fifo_perr", 19, 1 },
|
||||
{ "tx_fifo_perr", 18, 1 },
|
||||
{ "non_ipsec_tx_fifo3_perr", 17, 1 },
|
||||
{ "non_ipsec_tx_fifo2_perr", 16, 1 },
|
||||
{ "non_ipsec_tx_fifo1_perr", 15, 1 },
|
||||
{ "non_ipsec_tx_fifo0_perr", 14, 1 },
|
||||
{ "tp2mps_tx0", 13, 1 },
|
||||
{ "crypto2mps_tx0", 12, 1 },
|
||||
{ "tp2mps_tx1", 11, 1 },
|
||||
{ "crypto2mps_tx1", 10, 1 },
|
||||
{ "tp2mps_tx2", 9, 1 },
|
||||
{ "crypto2mps_tx2", 8, 1 },
|
||||
{ "tp2mps_tx3", 7, 1 },
|
||||
{ "crypto2mps_tx3", 6, 1 },
|
||||
{ "ncsi2mps", 5, 1 },
|
||||
{ "Ncsi_perr", 4, 1 },
|
||||
{ "TP_perr", 0, 4 },
|
||||
{ "MPS_TX_NCSI2MPS_CNT", 0x940c, 0 },
|
||||
{ "MPS_TX_PERR_ENABLE", 0x9410, 0 },
|
||||
{ "PortErrInt", 28, 1 },
|
||||
|
|
@ -10640,7 +10957,17 @@ struct reg_info t7_mps_regs[] = {
|
|||
{ "MPS_TX_DBG_CNT_CTL", 0x9478, 0 },
|
||||
{ "MPS_TX_DBG_CNT", 0x947c, 0 },
|
||||
{ "MPS_TX_INT2_ENABLE", 0x9498, 0 },
|
||||
{ "tx_fifo_perr", 4, 1 },
|
||||
{ "non_ipsec_tx_fifo3", 3, 1 },
|
||||
{ "non_ipsec_tx_fifo2", 2, 1 },
|
||||
{ "non_ipsec_tx_fifo1", 1, 1 },
|
||||
{ "non_ipsec_tx_fifo0", 0, 1 },
|
||||
{ "MPS_TX_INT2_CAUSE", 0x949c, 0 },
|
||||
{ "tx_fifo_perr", 4, 1 },
|
||||
{ "non_ipsec_tx_fifo3_perr", 3, 1 },
|
||||
{ "non_ipsec_tx_fifo2_perr", 2, 1 },
|
||||
{ "non_ipsec_tx_fifo1_perr", 1, 1 },
|
||||
{ "non_ipsec_tx_fifo0_perr", 0, 1 },
|
||||
{ "MPS_TX_PERR2_ENABLE", 0x94a0, 0 },
|
||||
{ "MPS_TX_INT3_ENABLE", 0x94a4, 0 },
|
||||
{ "MPS_TX_INT3_CAUSE", 0x94a8, 0 },
|
||||
|
|
@ -11064,6 +11391,7 @@ struct reg_info t7_mps_regs[] = {
|
|||
{ "MemSel", 1, 4 },
|
||||
{ "InjectDataErr", 0, 1 },
|
||||
{ "MPS_TRC_PERR_ENABLE", 0x9854, 0 },
|
||||
{ "PLErrEnb", 17, 1 },
|
||||
{ "MiscPerr", 16, 1 },
|
||||
{ "PktFifo", 8, 8 },
|
||||
{ "FiltMem", 0, 8 },
|
||||
|
|
@ -11093,34 +11421,39 @@ struct reg_info t7_mps_regs[] = {
|
|||
{ "TF4_perr_0", 8, 1 },
|
||||
{ "Perr_tf_in_ctl", 0, 8 },
|
||||
{ "MPS_TRC_INT_ENABLE2", 0xa4f4, 0 },
|
||||
{ "trc_tf_ecc", 24, 8 },
|
||||
{ "mps2mac_conv_trc_cerr", 22, 2 },
|
||||
{ "mps2mac_conv_trc", 18, 4 },
|
||||
{ "TF0_perr_1", 17, 1 },
|
||||
{ "TF1_perr_1", 16, 1 },
|
||||
{ "TF2_perr_1", 15, 1 },
|
||||
{ "TF3_perr_1", 14, 1 },
|
||||
{ "TF4_perr_1", 13, 1 },
|
||||
{ "TF0_perr_0", 12, 1 },
|
||||
{ "TF1_perr_0", 11, 1 },
|
||||
{ "TF2_perr_0", 10, 1 },
|
||||
{ "TF3_perr_0", 9, 1 },
|
||||
{ "TF4_perr_0", 8, 1 },
|
||||
{ "Perr_tf_in_ctl", 0, 8 },
|
||||
{ "tx2rx_dwn_conv_perr_pt3_cerr", 16, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt2_cerr", 15, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt1_cerr", 14, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt0_cerr", 13, 1 },
|
||||
{ "mps2mac_dwn_conv_perr_pt1_cerr", 12, 1 },
|
||||
{ "mps2mac_dwn_conv_perr_pt0_cerr", 11, 1 },
|
||||
{ "mac2mps_dwn_conv_perr_pt1_cerr", 10, 1 },
|
||||
{ "mac2mps_dwn_conv_perr_pt0_cerr", 9, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt3_perr", 8, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt2_perr", 7, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt1_perr", 6, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt0_perr", 5, 1 },
|
||||
{ "mac2mps_dwn_conv_perr_pt1_perr", 4, 1 },
|
||||
{ "mac2mps_dwn_conv_perr_pt0_perr", 3, 1 },
|
||||
{ "mps2mac_dwn_conv_perr_pt1_perr", 2, 1 },
|
||||
{ "mps2mac_dwn_conv_perr_pt0_perr", 1, 1 },
|
||||
{ "MPS_TRC_INT_CAUSE2", 0xa4f8, 0 },
|
||||
{ "trc_tf_ecc", 22, 8 },
|
||||
{ "mps2mac_conv_trc", 18, 4 },
|
||||
{ "TF0_perr_1", 17, 1 },
|
||||
{ "TF1_perr_1", 16, 1 },
|
||||
{ "TF2_perr_1", 15, 1 },
|
||||
{ "TF3_perr_1", 14, 1 },
|
||||
{ "TF4_perr_1", 13, 1 },
|
||||
{ "TF0_perr_0", 12, 1 },
|
||||
{ "TF1_perr_0", 11, 1 },
|
||||
{ "TF2_perr_0", 10, 1 },
|
||||
{ "TF3_perr_0", 9, 1 },
|
||||
{ "TF4_perr_0", 8, 1 },
|
||||
{ "Perr_tf_in_ctl", 0, 8 },
|
||||
{ "tx2rx_dwn_conv_perr_pt3_cerr", 16, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt2_cerr", 15, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt1_cerr", 14, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt0_cerr", 13, 1 },
|
||||
{ "mps2mac_dwn_conv_perr_pt1_cerr", 12, 1 },
|
||||
{ "mps2mac_dwn_conv_perr_pt0_cerr", 11, 1 },
|
||||
{ "mac2mps_dwn_conv_perr_pt1_cerr", 10, 1 },
|
||||
{ "mac2mps_dwn_conv_perr_pt0_cerr", 9, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt3_perr", 8, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt2_perr", 7, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt1_perr", 6, 1 },
|
||||
{ "tx2rx_dwn_conv_perr_pt0_perr", 5, 1 },
|
||||
{ "mac2mps_dwn_conv_perr_pt1_perr", 4, 1 },
|
||||
{ "mac2mps_dwn_conv_perr_pt0_perr", 3, 1 },
|
||||
{ "mps2mac_dwn_conv_perr_pt1_perr", 2, 1 },
|
||||
{ "mps2mac_dwn_conv_perr_pt0_perr", 1, 1 },
|
||||
{ "MPS_TRC_TIMESTAMP_L", 0xa4e8, 0 },
|
||||
{ "MPS_TRC_TIMESTAMP_H", 0xa4ec, 0 },
|
||||
{ "MPS_TRC_FILTER0_MATCH", 0x9c00, 0 },
|
||||
|
|
@ -11593,6 +11926,7 @@ struct reg_info t7_mps_regs[] = {
|
|||
{ "Lbport", 6, 5 },
|
||||
{ "Txport", 0, 6 },
|
||||
{ "MPS_STAT_PERR_INT_CAUSE_SRAM", 0x9614, 0 },
|
||||
{ "Rxpp", 29, 2 },
|
||||
{ "Rxbg", 27, 2 },
|
||||
{ "Rxpf", 22, 5 },
|
||||
{ "Txpf", 18, 4 },
|
||||
|
|
@ -11600,6 +11934,7 @@ struct reg_info t7_mps_regs[] = {
|
|||
{ "Lbport", 6, 5 },
|
||||
{ "Txport", 0, 6 },
|
||||
{ "MPS_STAT_PERR_ENABLE_SRAM", 0x9618, 0 },
|
||||
{ "Rxpp", 29, 2 },
|
||||
{ "Rxbg", 27, 2 },
|
||||
{ "Rxpf", 22, 5 },
|
||||
{ "Txpf", 18, 4 },
|
||||
|
|
@ -11678,14 +12013,20 @@ struct reg_info t7_mps_regs[] = {
|
|||
{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L", 0x96b8, 0 },
|
||||
{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H", 0x96bc, 0 },
|
||||
{ "MPS_STAT_PERR_INT_ENABLE_SRAM1", 0x96c0, 0 },
|
||||
{ "Rxvf", 5, 3 },
|
||||
{ "Txvf", 0, 5 },
|
||||
{ "Rxvf_cerr", 12, 4 },
|
||||
{ "Txvf_cerr", 8, 4 },
|
||||
{ "Rxvf_perr", 5, 3 },
|
||||
{ "Txvf_perr", 0, 5 },
|
||||
{ "MPS_STAT_PERR_INT_CAUSE_SRAM1", 0x96c4, 0 },
|
||||
{ "Rxvf", 5, 3 },
|
||||
{ "Txvf", 0, 5 },
|
||||
{ "Rxvf_cerr", 12, 4 },
|
||||
{ "Txvf_cerr", 8, 4 },
|
||||
{ "Rxvf_perr", 5, 3 },
|
||||
{ "Txvf_perr", 0, 5 },
|
||||
{ "MPS_STAT_PERR_ENABLE_SRAM1", 0x96c8, 0 },
|
||||
{ "Rxvf", 5, 3 },
|
||||
{ "Txvf", 0, 5 },
|
||||
{ "Rxvf_cerr", 12, 4 },
|
||||
{ "Txvf_cerr", 8, 4 },
|
||||
{ "Rxvf_perr", 5, 3 },
|
||||
{ "Txvf_perr", 0, 5 },
|
||||
{ "MPS_STAT_STOP_UPD_BG", 0x96cc, 0 },
|
||||
{ "MPS_STAT_STOP_UPD_PORT", 0x96d0, 0 },
|
||||
{ "PtLpbk", 8, 4 },
|
||||
|
|
@ -16266,9 +16607,9 @@ struct reg_info t7_smb_regs[] = {
|
|||
{ "DebugDataH", 16, 16 },
|
||||
{ "DebugDataL", 0, 16 },
|
||||
{ "SMB_PERR_EN", 0x19098, 0 },
|
||||
{ "MstTxFifo", 21, 1 },
|
||||
{ "MstRxFifo", 19, 1 },
|
||||
{ "SlvFifo", 18, 1 },
|
||||
{ "MstTxFifo", 22, 1 },
|
||||
{ "MstRxFifo", 21, 1 },
|
||||
{ "SlvFifo", 20, 1 },
|
||||
{ "MstTxFifoPerrEn", 2, 1 },
|
||||
{ "MstRxFifoPerrEn", 1, 1 },
|
||||
{ "SlvFifoPerrEn", 0, 1 },
|
||||
|
|
@ -22731,11 +23072,11 @@ struct reg_info t7_mac_t7_regs[] = {
|
|||
{ "MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_1", 0x38210, 0 },
|
||||
{ "MAC_MTIP_MAC400G_0_MTIP_FRM_LENGTH", 0x38214, 0 },
|
||||
{ "MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_SECTIONS", 0x3821c, 0 },
|
||||
{ "AVAIL", 16, 16 },
|
||||
{ "EMPTY", 0, 16 },
|
||||
{ "EMPTY", 16, 16 },
|
||||
{ "AVAIL", 0, 16 },
|
||||
{ "MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_SECTIONS", 0x38220, 0 },
|
||||
{ "AVAIL", 16, 16 },
|
||||
{ "EMPTY", 0, 16 },
|
||||
{ "EMPTY", 16, 16 },
|
||||
{ "AVAIL", 0, 16 },
|
||||
{ "MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_ALMOST_F_E", 0x38224, 0 },
|
||||
{ "AlmstFull", 16, 16 },
|
||||
{ "AlmstEmpty", 0, 16 },
|
||||
|
|
@ -26677,7 +27018,6 @@ struct reg_info t7_arm_regs[] = {
|
|||
{ "dftramhold", 1, 1 },
|
||||
{ "dftcgen", 0, 1 },
|
||||
{ "ARM_PLM_RID_CFG", 0x4703c, 0 },
|
||||
{ "ARM_PLM_EROM_CFG", 0x47040, 0 },
|
||||
{ "ARM_PL_ARM_HDR_CFG", 0x4704c, 0 },
|
||||
{ "ARM_MBISTACK", 0x477d4, 0 },
|
||||
{ "ARM_MBISTADDR", 0x477d8, 0 },
|
||||
|
|
@ -26919,12 +27259,9 @@ struct reg_info t7_mc_t70_regs[] = {
|
|||
{ "ECC_CE_INT_CAUSE", 2, 1 },
|
||||
{ "ECC_UE_INT_CAUSE", 1, 1 },
|
||||
{ "PERR_INT_CAUSE", 0, 1 },
|
||||
{ "MC_P_ECC_UE_INT_ENABLE", 0x49324, 0 },
|
||||
{ "MC_P_ECC_UE_INT_CAUSE", 0x49328, 0 },
|
||||
{ "MC_P_ECC_STATUS", 0x4932c, 0 },
|
||||
{ "ECC_CECNT", 16, 16 },
|
||||
{ "ECC_UECNT", 0, 16 },
|
||||
{ "MC_P_PHY_CTRL", 0x49330, 0 },
|
||||
{ "MC_P_STATIC_CFG_STATUS", 0x49334, 0 },
|
||||
{ "DfiFreqRatio", 27, 1 },
|
||||
{ "STATIC_PP64", 26, 1 },
|
||||
|
|
@ -27170,12 +27507,9 @@ struct reg_info t7_mc_t71_regs[] = {
|
|||
{ "ECC_CE_INT_CAUSE", 2, 1 },
|
||||
{ "ECC_UE_INT_CAUSE", 1, 1 },
|
||||
{ "PERR_INT_CAUSE", 0, 1 },
|
||||
{ "MC_P_ECC_UE_INT_ENABLE", 0x59324, 0 },
|
||||
{ "MC_P_ECC_UE_INT_CAUSE", 0x59328, 0 },
|
||||
{ "MC_P_ECC_STATUS", 0x5932c, 0 },
|
||||
{ "ECC_CECNT", 16, 16 },
|
||||
{ "ECC_UECNT", 0, 16 },
|
||||
{ "MC_P_PHY_CTRL", 0x59330, 0 },
|
||||
{ "MC_P_STATIC_CFG_STATUS", 0x59334, 0 },
|
||||
{ "DfiFreqRatio", 27, 1 },
|
||||
{ "STATIC_PP64", 26, 1 },
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue