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smartpqi: update to version 4660.0.2002

Browse source 
This updates the smartpqi driver to Microchip's
latest available public release.

Reviewed by: imp
Approved by: imp

Sponsored by: Microchip Technology Inc.

Differential Revision: https://reviews.freebsd.org/D52507

(cherry picked from commit c558eca479)
This commit is contained in:
John Hall 2025-08-28 16:11:02 -05:00
parent 653099bcc1
commit ec98cb5686
19 changed files with 725 additions and 625 deletions
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88
share/man/man4/smartpqi.4
View file

@ -1,4 +1,4 @@
.\" Copyright (C) 2019-2023, Microchip Technology Inc. and its subsidiaries
.\" Copyright (C) 2019-2025, Microchip Technology Inc. and its subsidiaries
.\" Copyright (C) 2016-2018, Microsemi Corporation
.\" Copyright (C) 2016, PMC-Sierra, Inc.
.\" Written by John Hall <john.hall@microchip.com>
@ -24,8 +24,8 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.Dd August 24, 2023
.Dt SMARTPQI 4
.Dd August 28, 2025
.Dt SMARTPQI 4 amd64
.Os
.Sh NAME
.Nm smartpqi
@ -48,7 +48,7 @@ smartpqi_load="YES"
The
.Nm
driver provides support for Microchip Technology Inc. / Adaptec SmartRaid and
SmartHBA SATA/SAS/NVME PCIe controllers
SmartHBA SATA/SAS/NVMe PCIe controllers
.Sh HARDWARE
Controllers supported by the
.Nm
@ -63,6 +63,86 @@ Adaptec SmartRaid and SmartHBA Controllers
OEM Controllers based on the Microchip Technology Inc. SmartROC
and SmartIOC Chipsets
.El
.Sh DEBUGGING
Driver diagnostic printing is controlled in
.Xr loader.conf 5
by using the global
.Va hw.smartpqi.debug_level
tunable.
.Pp
The
.Va debug_level
variable is set with an integer value.
The default value is 0x0060 (warn && error).
.Pp
The following levels are available:
.Bl -column "FlagXX" "NameXXXX" "Description" -offset indent
.It Em Flag Ta Em Name Ta Em Description
.It 0x0001 Ta init Ta System initialization operations
.It 0x0002 Ta info Ta Basic information
.It 0x0004 Ta function Ta Used to show function entry and exit
.It 0x0008 Ta io Ta Logging data from controller
.It 0x0010 Ta discovery Ta Device discovery
.It 0x0020 Ta warning Ta Operational warnings
.It 0x0040 Ta error Ta Parameter errors and programming bugs
.It 0x0080 Ta note Ta More detailed information
.El
.Sh DEVICE HINTS
The following tunable values can be set in
.Pa /boot/device.hints
to control the behavior of the
.Nm
driver.
These hints are specified as:
.Bd -literal -offset indent
hint.smartpqi.<unit>.<variable>=<value>
.Ed
.Pp
The supported variables are:
.Bl -tag -width ".Va aio_raid1_write_disable"
.It Va stream_disable
If set to 0, disables Stream Detection.
.Pp
Default is (enabled).
.It Va sata_unique_wwn_disable
If set to 0, disables SATA Unique World Wide Number.
.Pp
Default is (enabled).
.It Va aio_raid1_write_disable
If set to 0, disables acceleration of RAID1 writes
.Pp
Default is (enabled).
.It Va aio_raid5_write_disable
If set to 0, disables acceleration of RAID5 writes
.Pp
Default is (enabled).
.It Va aio_raid6_write_disable
If set to 0, disables acceleration of RAID6 writes
.Pp
Default is (enabled).
.It Va queue_depth
Sets queue depth for the controller. If the queue depth value
is greater than the maximum supported queue size of the driver or
controller, it will be set to the lowest size. If the queue
depth value is lower than the minimum queue depth then this will
be set to the minimum queue depth.
.Pp
Default is driver-determined.
.It Va sg_count
Sets the scatter gather (sg) count. If this sg count is greater
than maximum sg count it will be set to the maximum sg count.
If this sg count is less than minimum sg count it will be set to
the minimum sg count.
.Pp
Default is driver-determined.
.El
.Pp
For example, to disable Stream Detection on the first controller, add
the following line to
.Pa /boot/device.hints :
.Bd -literal -offset indent
hint.smartpqi.0.stream_disable="0"
.Ed
.Sh FILES
.Bl -tag -width /boot/kernel/smartpqi.ko -compact
.It Pa /dev/smartpqi?

53
sys/dev/smartpqi/smartpqi_cam.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -71,7 +71,6 @@ update_sim_properties(struct cam_sim *sim, struct ccb_pathinq *cpi)
cpi->hba_subvendor = pci_get_subvendor(dev);
cpi->hba_subdevice = pci_get_subdevice(dev);
DBG_FUNC("OUT\n");
}
@ -154,10 +153,6 @@ os_remove_device(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
}
xpt_async(AC_LOST_DEVICE, tmppath, NULL);
xpt_free_path(tmppath);
/* softs->device_list[device->target][device->lun] = NULL; */
int index = pqisrc_find_device_list_index(softs,device);
if (index >= 0 && index < PQI_MAX_DEVICES)
softs->dev_list[index] = NULL;
pqisrc_free_device(softs, device);
}
@ -335,7 +330,7 @@ os_io_response_success(rcb_t *rcb)
static void
copy_sense_data_to_csio(struct ccb_scsiio *csio,
uint8_t *sense_data, uint16_t sense_data_len)
uint8_t const *sense_data, uint16_t sense_data_len)
{
DBG_IO("IN csio = %p\n", csio);
@ -740,7 +735,7 @@ smartpqi_target_rescan(struct pqisrc_softstate *softs)
/* if(softs->device_list[target][lun]){ */
if(softs->dev_list[index] != NULL) {
device = softs->dev_list[index];
DBG_INFO("calling smartpqi_lun_rescan with TL = %d:%d\n",device->target,device->lun);
DBG_INFO("calling smartpqi_lun_rescan with T%d:L%d\n",device->target,device->lun);
smartpqi_lun_rescan(softs, device->target, device->lun);
}
}
@ -821,7 +816,6 @@ pqisrc_io_start(struct cam_sim *sim, union ccb *ccb)
if (index == INVALID_ELEM) {
ccb->ccb_h.status = CAM_DEV_NOT_THERE;
DBG_INFO("Invalid index/device!!!, Device BTL %u:%d:%d\n", softs->bus_id, target, lun);
return ENXIO;
}
@ -850,7 +844,7 @@ pqisrc_io_start(struct cam_sim *sim, union ccb *ccb)
}
/* Check device reset */
if (DEVICE_RESET(dvp)) {
ccb->ccb_h.status = CAM_SCSI_BUSY | CAM_REQ_INPROG | CAM_BUSY;
ccb->ccb_h.status = CAM_BUSY;
DBG_WARN("Device %d reset returned busy\n", ccb->ccb_h.target_id);
return EBUSY;
}
@ -915,7 +909,7 @@ pqisrc_io_start(struct cam_sim *sim, union ccb *ccb)
}
static inline int
pqi_tmf_status_to_bsd_tmf_status(int pqi_status, rcb_t *rcb)
pqi_tmf_status_to_bsd_tmf_status(int pqi_status, rcb_t const *rcb)
{
if (PQI_STATUS_SUCCESS == pqi_status &&
PQI_STATUS_SUCCESS == rcb->status)
@ -931,7 +925,7 @@ static int
pqisrc_scsi_abort_task(pqisrc_softstate_t *softs, union ccb *ccb)
{
rcb_t *rcb = NULL;
struct ccb_hdr *ccb_h = &ccb->ccb_h;
struct ccb_hdr const *ccb_h = &ccb->ccb_h;
rcb_t *prcb = ccb->ccb_h.sim_priv.entries[0].ptr;
uint32_t tag;
int rval;
@ -971,7 +965,7 @@ error_tmf:
static int
pqisrc_scsi_abort_task_set(pqisrc_softstate_t *softs, union ccb *ccb)
{
struct ccb_hdr *ccb_h = &ccb->ccb_h;
struct ccb_hdr const *ccb_h = &ccb->ccb_h;
rcb_t *rcb = NULL;
uint32_t tag;
int rval;
@ -1013,7 +1007,7 @@ pqisrc_target_reset( pqisrc_softstate_t *softs, union ccb *ccb)
{
/* pqi_scsi_dev_t *devp = softs->device_list[ccb->ccb_h.target_id][ccb->ccb_h.target_lun]; */
struct ccb_hdr *ccb_h = &ccb->ccb_h;
struct ccb_hdr const *ccb_h = &ccb->ccb_h;
rcb_t *rcb = NULL;
uint32_t tag;
int rval;
@ -1069,7 +1063,7 @@ static void
smartpqi_cam_action(struct cam_sim *sim, union ccb *ccb)
{
struct pqisrc_softstate *softs = cam_sim_softc(sim);
struct ccb_hdr *ccb_h = &ccb->ccb_h;
struct ccb_hdr const *ccb_h = &ccb->ccb_h;
DBG_FUNC("IN\n");
@ -1209,22 +1203,19 @@ smartpqi_async(void *callback_arg, u_int32_t code,
}
uint32_t t_id = cgd->ccb_h.target_id;
/* if (t_id <= (PQI_CTLR_INDEX - 1)) { */
if (t_id >= PQI_CTLR_INDEX) {
if (softs != NULL) {
/* pqi_scsi_dev_t *dvp = softs->device_list[t_id][cgd->ccb_h.target_lun]; */
int lun = cgd->ccb_h.target_lun;
int index = pqisrc_find_btl_list_index(softs,softs->bus_id,t_id,lun);
if (index != INVALID_ELEM) {
pqi_scsi_dev_t *dvp = softs->dev_list[index];
if (dvp == NULL) {
DBG_ERR("Target is null, target id=%u\n", t_id);
break;
}
smartpqi_adjust_queue_depth(path, dvp->queue_depth);
}
}
}
if (softs != NULL) {
/* pqi_scsi_dev_t *dvp = softs->device_list[t_id][cgd->ccb_h.target_lun]; */
int lun = cgd->ccb_h.target_lun;
int index = pqisrc_find_btl_list_index(softs,softs->bus_id,t_id,lun);
if (index != INVALID_ELEM) {
pqi_scsi_dev_t const *dvp = softs->dev_list[index];
if (dvp == NULL) {
DBG_ERR("Target is null, target id=%u\n", t_id);
break;
}
smartpqi_adjust_queue_depth(path, dvp->queue_depth);
}
}
break;
}
default:

4
sys/dev/smartpqi/smartpqi_cmd.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -35,7 +35,7 @@ pqisrc_submit_cmnd(pqisrc_softstate_t *softs, ib_queue_t *ib_q, void *req)
{
char *slot = NULL;
uint32_t offset;
iu_header_t *hdr = (iu_header_t *)req;
iu_header_t const *hdr = (iu_header_t *)req;
/*TODO : Can be fixed a size copying of IU ? */
uint32_t iu_len = hdr->iu_length + 4 ; /* header size */
int i = 0;

371
sys/dev/smartpqi/smartpqi_controllers.h Normal file
View file

@ -0,0 +1,371 @@
/*-
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Supported controllers
*/
struct pqi_ident
{
u_int16_t vendor;
u_int16_t device;
u_int16_t subvendor;
u_int16_t subdevice;
int hwif;
char *desc;
} pqi_identifiers[] = {
/* (MSCC PM8205 8x12G based) */
{0x9005, 0x028f, 0x103c, 0x600, PQI_HWIF_SRCV, "P408i-p SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x601, PQI_HWIF_SRCV, "P408e-p SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x602, PQI_HWIF_SRCV, "P408i-a SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x603, PQI_HWIF_SRCV, "P408i-c SR Gen10"},
{0x9005, 0x028f, 0x1028, 0x1FE0, PQI_HWIF_SRCV, "SmartRAID 3162-8i/eDell"},
{0x9005, 0x028f, 0x9005, 0x608, PQI_HWIF_SRCV, "SmartRAID 3162-8i/e"},
{0x9005, 0x028f, 0x103c, 0x609, PQI_HWIF_SRCV, "P408i-sb SR G10"},
/* (MSCC PM8225 8x12G based) */
{0x9005, 0x028f, 0x103c, 0x650, PQI_HWIF_SRCV, "E208i-p SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x651, PQI_HWIF_SRCV, "E208e-p SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x652, PQI_HWIF_SRCV, "E208i-c SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x654, PQI_HWIF_SRCV, "E208i-a SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x655, PQI_HWIF_SRCV, "P408e-m SR Gen10"},
{0x9005, 0x028f, 0x9005, 0x659, PQI_HWIF_SRCV, "2100C8iOXS"},
/* (MSCC PM8221 8x12G based) */
{0x9005, 0x028f, 0x103c, 0x700, PQI_HWIF_SRCV, "P204i-c SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x701, PQI_HWIF_SRCV, "P204i-b SR Gen10"},
{0x9005, 0x028f, 0x193d, 0x1104, PQI_HWIF_SRCV, "UN RAID P2404-Mf-4i-2GB"},
{0x9005, 0x028f, 0x193d, 0x1106, PQI_HWIF_SRCV, "UN RAID P2404-Mf-4i-1GB"},
{0x9005, 0x028f, 0x193d, 0x1108, PQI_HWIF_SRCV, "UN RAID P4408-Ma-8i-2GB"},
{0x9005, 0x028f, 0x193d, 0x1109, PQI_HWIF_SRCV, "UN RAID P4408-Mr-8i-2GB"},
/* (MSCC PM8204 8x12G based) */
{0x9005, 0x028f, 0x9005, 0x800, PQI_HWIF_SRCV, "SmartRAID 3154-8i"},
{0x9005, 0x028f, 0x9005, 0x801, PQI_HWIF_SRCV, "SmartRAID 3152-8i"},
{0x9005, 0x028f, 0x9005, 0x802, PQI_HWIF_SRCV, "SmartRAID 3151-4i"},
{0x9005, 0x028f, 0x9005, 0x803, PQI_HWIF_SRCV, "SmartRAID 3101-4i"},
{0x9005, 0x028f, 0x9005, 0x804, PQI_HWIF_SRCV, "SmartRAID 3154-8e"},
{0x9005, 0x028f, 0x9005, 0x805, PQI_HWIF_SRCV, "SmartRAID 3102-8i"},
{0x9005, 0x028f, 0x9005, 0x806, PQI_HWIF_SRCV, "SmartRAID 3100"},
{0x9005, 0x028f, 0x9005, 0x807, PQI_HWIF_SRCV, "SmartRAID 3162-8i"},
{0x9005, 0x028f, 0x152d, 0x8a22, PQI_HWIF_SRCV, "QS-8204-8i"},
{0x9005, 0x028f, 0x193d, 0xf460, PQI_HWIF_SRCV, "UN RAID P460-M4"},
{0x9005, 0x028f, 0x193d, 0xf461, PQI_HWIF_SRCV, "UN RAID P460-B4"},
{0x9005, 0x028f, 0x1bd4, 0x004b, PQI_HWIF_SRCV, "PM8204-2GB"},
{0x9005, 0x028f, 0x1bd4, 0x004c, PQI_HWIF_SRCV, "PM8204-4GB"},
{0x9005, 0x028f, 0x1ff9, 0x004b, PQI_HWIF_SRCV, "RAID PM8204-2GB"},
{0x9005, 0x028f, 0x1ff9, 0x004c, PQI_HWIF_SRCV, "RAID PM8204-4GB"},
{0x9005, 0x028f, 0x193d, 0x0462, PQI_HWIF_SRCV, "UN RAID P460-Mr1-8i-4GB"},
{0x9005, 0x028f, 0x193d, 0x1105, PQI_HWIF_SRCV, "UN RAID P4408-Mf-8i-2GB"},
{0x9005, 0x028f, 0x193d, 0x1107, PQI_HWIF_SRCV, "UN RAID P4408-Mf-8i-4GB"},
{0x9005, 0x028f, 0x193d, 0x1110, PQI_HWIF_SRCV, "UN RAID P4408-Mr-2"},
{0x9005, 0x028f, 0x1d8d, 0x800, PQI_HWIF_SRCV, "Fiberhome SmartRAID AIS-8204-8i"},
{0x9005, 0x028f, 0x9005, 0x0808, PQI_HWIF_SRCV, "SmartRAID 3101E-4i"},
{0x9005, 0x028f, 0x9005, 0x0809, PQI_HWIF_SRCV, "SmartRAID 3102E-8i"},
{0x9005, 0x028f, 0x9005, 0x080a, PQI_HWIF_SRCV, "SmartRAID 3152-8i/N"},
{0x9005, 0x028f, 0x1cc4, 0x0101, PQI_HWIF_SRCV, "Ramaxel FBGF-RAD PM8204"},
{0x9005, 0x028f, 0x1f3a, 0x0104, PQI_HWIF_SRCV, "PL SmartROC PM8204"},
{0x9005, 0x028f, 0x1f51, 0x1043, PQI_HWIF_SRCV, "SmartRAID P7502-8i"},
{0x9005, 0x028f, 0x1f51, 0x1045, PQI_HWIF_SRCV, "SmartRAID P7504-8i"},
{0x9005, 0x028f, 0x1f51, 0x1011, PQI_HWIF_SRCV, "SmartRAID P7504N-8i"},
{0x9005, 0x028f, 0x207d, 0x4140, PQI_HWIF_SRCV, "HRDT TrustRAID D3152s-8i"},
{0x9005, 0x028f, 0x207d, 0x4240, PQI_HWIF_SRCV, "HRDT TrustRAID D3154s-8i"},
/* (MSCC PM8222 8x12G based) */
{0x9005, 0x028f, 0x9005, 0x900, PQI_HWIF_SRCV, "SmartHBA 2100-8i"},
{0x9005, 0x028f, 0x9005, 0x901, PQI_HWIF_SRCV, "SmartHBA 2100-4i"},
{0x9005, 0x028f, 0x9005, 0x902, PQI_HWIF_SRCV, "HBA 1100-8i"},
{0x9005, 0x028f, 0x9005, 0x903, PQI_HWIF_SRCV, "HBA 1100-4i"},
{0x9005, 0x028f, 0x9005, 0x904, PQI_HWIF_SRCV, "SmartHBA 2100-8e"},
{0x9005, 0x028f, 0x9005, 0x905, PQI_HWIF_SRCV, "HBA 1100-8e"},
{0x9005, 0x028f, 0x9005, 0x906, PQI_HWIF_SRCV, "SmartHBA 2100-4i4e"},
{0x9005, 0x028f, 0x9005, 0x907, PQI_HWIF_SRCV, "HBA 1100"},
{0x9005, 0x028f, 0x9005, 0x908, PQI_HWIF_SRCV, "SmartHBA 2100"},
{0x9005, 0x028f, 0x9005, 0x90a, PQI_HWIF_SRCV, "SmartHBA 2100A-8i"},
{0x9005, 0x028f, 0x193d, 0x8460, PQI_HWIF_SRCV, "UN HBA H460-M1"},
{0x9005, 0x028f, 0x193d, 0x8461, PQI_HWIF_SRCV, "UN HBA H460-B1"},
{0x9005, 0x028f, 0x193d, 0x8462, PQI_HWIF_SRCV, "UN HBA H460-Mr1-8i"},
{0x9005, 0x028f, 0x193d, 0xc460, PQI_HWIF_SRCV, "UN RAID P460-M2"},
{0x9005, 0x028f, 0x193d, 0xc461, PQI_HWIF_SRCV, "UN RAID P460-B2"},
{0x9005, 0x028f, 0x1bd4, 0x004a, PQI_HWIF_SRCV, "PM8222-SHBA"},
{0x9005, 0x028f, 0x1ff9, 0x004a, PQI_HWIF_SRCV, "PM8222-SHBA"},
{0x9005, 0x028f, 0x13fe, 0x8312, PQI_HWIF_SRCV, "MIC-8312BridgeB"},
{0x9005, 0x028f, 0x1bd4, 0x004f, PQI_HWIF_SRCV, "PM8222-HBA"},
{0x9005, 0x028f, 0x1ff9, 0x004f, PQI_HWIF_SRCV, "PM8222-HBA"},
{0x9005, 0x028f, 0x1d8d, 0x908, PQI_HWIF_SRCV, "Fiberhome SmartHBA AIS-8222-8i"},
{0x9005, 0x028f, 0x1bd4, 0x006C, PQI_HWIF_SRCV, "RS0800M5E8i"},
{0x9005, 0x028f, 0x1bd4, 0x006D, PQI_HWIF_SRCV, "RS0800M5H8i"},
{0x9005, 0x028f, 0x1ff9, 0x006C, PQI_HWIF_SRCV, "RS0800M5E8i"},
{0x9005, 0x028f, 0x1ff9, 0x006D, PQI_HWIF_SRCV, "RS0800M5H8i"},
{0x9005, 0x028f, 0x1cc4, 0x0201, PQI_HWIF_SRCV, "Ramaxel FBGF-RAD PM8222"},
{0x9005, 0x028f, 0x1f51, 0x1044, PQI_HWIF_SRCV, "SmartHBA P6500-8i"},
{0x9005, 0x028f, 0x1f3f, 0x0610, PQI_HWIF_SRCV, "3SNIC SSSRAID 3S610"},
{0x9005, 0x028f, 0x207d, 0x4840, PQI_HWIF_SRCV, "HRDT TrustHBA H3100s-8i"},
/* (SRCx MSCC FVB 24x12G based) */
{0x9005, 0x028f, 0x103c, 0x1001, PQI_HWIF_SRCV, "MSCC FVB"},
/* (MSCC PM8241 24x12G based) */
/* (MSCC PM8242 24x12G based) */
{0x9005, 0x028f, 0x152d, 0x8a37, PQI_HWIF_SRCV, "QS-8242-24i"},
{0x9005, 0x028f, 0x9005, 0x1300, PQI_HWIF_SRCV, "HBA 1100-8i8e"},
{0x9005, 0x028f, 0x9005, 0x1301, PQI_HWIF_SRCV, "HBA 1100-24i"},
{0x9005, 0x028f, 0x9005, 0x1302, PQI_HWIF_SRCV, "SmartHBA 2100-8i8e"},
{0x9005, 0x028f, 0x9005, 0x1303, PQI_HWIF_SRCV, "SmartHBA 2100-24i"},
{0x9005, 0x028f, 0x105b, 0x1321, PQI_HWIF_SRCV, "8242-24i"},
{0x9005, 0x028f, 0x1bd4, 0x0045, PQI_HWIF_SRCV, "SMART-HBA 8242-24i"},
{0x9005, 0x028f, 0x1ff9, 0x0045, PQI_HWIF_SRCV, "SMART-HBA 8242-24i"},
{0x9005, 0x028f, 0x1bd4, 0x006B, PQI_HWIF_SRCV, "RS0800M5H24i"},
{0x9005, 0x028f, 0x1bd4, 0x0070, PQI_HWIF_SRCV, "RS0800M5E24i"},
{0x9005, 0x028f, 0x1ff9, 0x006B, PQI_HWIF_SRCV, "RS0800M5H24i"},
{0x9005, 0x028f, 0x1ff9, 0x0070, PQI_HWIF_SRCV, "RS0800M5E24i"},
/* (MSCC PM8236 16x12G based) */
{0x9005, 0x028f, 0x152d, 0x8a24, PQI_HWIF_SRCV, "QS-8236-16i"},
{0x9005, 0x028f, 0x9005, 0x1380, PQI_HWIF_SRCV, "SmartRAID 3154-16i"},
{0x9005, 0x028f, 0x1bd4, 0x0046, PQI_HWIF_SRCV, "RAID 8236-16i"},
{0x9005, 0x028f, 0x1ff9, 0x0046, PQI_HWIF_SRCV, "RAID 8236-16i"},
{0x9005, 0x028f, 0x1d8d, 0x806, PQI_HWIF_SRCV, "Fiberhome SmartRAID AIS-8236-16i"},
{0x9005, 0x028f, 0x1cf2, 0x0B27, PQI_HWIF_SRCV, "ZTE SmartROC3100 SDPSA/B-18i 4G"},
{0x9005, 0x028f, 0x1cf2, 0x0B45, PQI_HWIF_SRCV, "ZTE SmartROC3100 SDPSA/B_L-18i 2G"},
{0x9005, 0x028f, 0x1cf2, 0x5445, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM241-18i 2G"},
{0x9005, 0x028f, 0x1cf2, 0x5446, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM242-18i 4G"},
{0x9005, 0x028f, 0x1cf2, 0x5449, PQI_HWIF_SRCV, "ZTE SmartROC3100 RS241-18i 2G"},
{0x9005, 0x028f, 0x1cf2, 0x544A, PQI_HWIF_SRCV, "ZTE SmartROC3100 RS242-18i 4G"},
{0x9005, 0x028f, 0x1cf2, 0x544D, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM241B-18i 2G"},
{0x9005, 0x028f, 0x1cf2, 0x544E, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM242B-18i 4G"},
{0x9005, 0x028f, 0x1bd4, 0x006F, PQI_HWIF_SRCV, "RS0804M5R16i"},
{0x9005, 0x028f, 0x1ff9, 0x006F, PQI_HWIF_SRCV, "RS0804M5R16i"},
{0x9005, 0x028f, 0x1f51, 0x1010, PQI_HWIF_SRCV, "SmartRAID P7504N-16i"},
/* (MSCC PM8237 24x12G based) */
{0x9005, 0x028f, 0x103c, 0x1100, PQI_HWIF_SRCV, "P816i-a SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x1101, PQI_HWIF_SRCV, "P416ie-m SR G10"},
/* (MSCC PM8238 16x12G based) */
{0x9005, 0x028f, 0x152d, 0x8a23, PQI_HWIF_SRCV, "QS-8238-16i"},
{0x9005, 0x028f, 0x9005, 0x1280, PQI_HWIF_SRCV, "HBA 1100-16i"},
{0x9005, 0x028f, 0x9005, 0x1281, PQI_HWIF_SRCV, "HBA 1100-16e"},
{0x9005, 0x028f, 0x105b, 0x1211, PQI_HWIF_SRCV, "8238-16i"},
{0x9005, 0x028f, 0x1bd4, 0x0048, PQI_HWIF_SRCV, "SMART-HBA 8238-16i"},
{0x9005, 0x028f, 0x1ff9, 0x0048, PQI_HWIF_SRCV, "SMART-HBA 8238-16i"},
{0x9005, 0x028f, 0x9005, 0x1282, PQI_HWIF_SRCV, "SmartHBA 2100-16i"},
{0x9005, 0x028f, 0x1d8d, 0x916, PQI_HWIF_SRCV, "Fiberhome SmartHBA AIS-8238-16i"},
{0x9005, 0x028f, 0x1458, 0x1000, PQI_HWIF_SRCV, "GIGABYTE SmartHBA CLN1832"},
{0x9005, 0x028f, 0x1cf2, 0x0B29, PQI_HWIF_SRCV, "ZTE SmartIOC2100 SDPSA/B_I-18i"},
{0x9005, 0x028f, 0x1cf2, 0x5447, PQI_HWIF_SRCV, "ZTE SmartIOC2100 RM243-18i"},
{0x9005, 0x028f, 0x1cf2, 0x544B, PQI_HWIF_SRCV, "ZTE SmartIOC2100 RS243-18i"},
{0x9005, 0x028f, 0x1cf2, 0x544F, PQI_HWIF_SRCV, "ZTE SmartIOC2100 RM243B-18i"},
{0x9005, 0x028f, 0x1bd4, 0x0071, PQI_HWIF_SRCV, "RS0800M5H16i"},
{0x9005, 0x028f, 0x1bd4, 0x0072, PQI_HWIF_SRCV, "RS0800M5E16i"},
{0x9005, 0x028f, 0x1ff9, 0x0071, PQI_HWIF_SRCV, "RS0800M5H16i"},
{0x9005, 0x028f, 0x1ff9, 0x0072, PQI_HWIF_SRCV, "RS0800M5E16i"},
{0x9005, 0x028f, 0x1018, 0x8238, PQI_HWIF_SRCV, "Ramaxel SmartHBA RX8238-16i"},
/* (MSCC PM8240 24x12G based) */
{0x9005, 0x028f, 0x152d, 0x8a36, PQI_HWIF_SRCV, "QS-8240-24i"},
{0x9005, 0x028f, 0x9005, 0x1200, PQI_HWIF_SRCV, "SmartRAID 3154-24i"},
{0x9005, 0x028f, 0x9005, 0x1201, PQI_HWIF_SRCV, "SmartRAID 3154-8i16e"},
{0x9005, 0x028f, 0x9005, 0x1202, PQI_HWIF_SRCV, "SmartRAID 3154-8i8e"},
{0x9005, 0x028f, 0x1bd4, 0x0047, PQI_HWIF_SRCV, "RAID 8240-24i"},
{0x9005, 0x028f, 0x1ff9, 0x0047, PQI_HWIF_SRCV, "RAID 8240-24i"},
{0x9005, 0x028f, 0x1dfc, 0x3161, PQI_HWIF_SRCV, "NTCOM SAS3 RAID-24i"},
{0x9005, 0x028f, 0x1F0C, 0x3161, PQI_HWIF_SRCV, "NT RAID 3100-24i"},
/* Huawei ID's */
{0x9005, 0x028f, 0x19e5, 0xd227, PQI_HWIF_SRCV, "SR465C-M 4G"},
{0x9005, 0x028f, 0x19e5, 0xd22a, PQI_HWIF_SRCV, "SR765-M"},
{0x9005, 0x028f, 0x19e5, 0xd228, PQI_HWIF_SRCV, "SR455C-M 2G"},
{0x9005, 0x028f, 0x19e5, 0xd22c, PQI_HWIF_SRCV, "SR455C-M 4G"},
{0x9005, 0x028f, 0x19e5, 0xd229, PQI_HWIF_SRCV, "SR155-M"},
{0x9005, 0x028f, 0x19e5, 0xd22b, PQI_HWIF_SRCV, "SR455C-ME 4G"},
/* (MSCC PM8252 8x12G based) */
{0x9005, 0x028f, 0x193d, 0x110b, PQI_HWIF_SRCV, "UN HBA H4508-Mf-8i"},
{0x9005, 0x028f, 0x1bd4, 0x0052, PQI_HWIF_SRCV, "MT0801M6E"},
{0x9005, 0x028f, 0x1bd4, 0x0054, PQI_HWIF_SRCV, "MT0800M6H"},
{0x9005, 0x028f, 0x1bd4, 0x0086, PQI_HWIF_SRCV, "RT0800M7E"},
{0x9005, 0x028f, 0x1bd4, 0x0087, PQI_HWIF_SRCV, "RT0800M7H"},
{0x9005, 0x028f, 0x1ff9, 0x0052, PQI_HWIF_SRCV, "MT0801M6E"},
{0x9005, 0x028f, 0x1ff9, 0x0054, PQI_HWIF_SRCV, "MT0800M6H"},
{0x9005, 0x028f, 0x1BD4, 0x00a3, PQI_HWIF_SRCV, "RT0800M6E2i"},
{0x9005, 0x028f, 0x1ff9, 0x00a3, PQI_HWIF_SRCV, "RT0800M6E2i"},
{0x9005, 0x028f, 0x1ff9, 0x0086, PQI_HWIF_SRCV, "RT0800M7E"},
{0x9005, 0x028f, 0x1ff9, 0x0087, PQI_HWIF_SRCV, "RT0800M7H"},
{0x9005, 0x028f, 0x1f51, 0x1001, PQI_HWIF_SRCV, "SmartHBA P6600-8i"},
{0x9005, 0x028f, 0x1f51, 0x1003, PQI_HWIF_SRCV, "SmartHBA P6600-8e"},
{0x9005, 0x028f, 0x9005, 0x1460, PQI_HWIF_SRCV, "HBA 1200"},
{0x9005, 0x028f, 0x9005, 0x1461, PQI_HWIF_SRCV, "SmartHBA 2200"},
{0x9005, 0x028f, 0x9005, 0x1462, PQI_HWIF_SRCV, "HBA 1200-8i"},
{0x9005, 0x028f, 0x1d49, 0x0222, PQI_HWIF_SRCV, "4450-8i HBA"},
{0x9005, 0x028f, 0x207d, 0x4044, PQI_HWIF_SRCV, "HRDT TrustHBA H4100-8i"},
{0x9005, 0x028f, 0x207d, 0x4054, PQI_HWIF_SRCV, "HRDT TrustHBA H4100-8e"},
/* (MSCC PM8254 32x12G based) */
{0x9005, 0x028f, 0x1bd4, 0x0051, PQI_HWIF_SRCV, "MT0804M6R"},
{0x9005, 0x028f, 0x1bd4, 0x0053, PQI_HWIF_SRCV, "MT0808M6R"},
{0x9005, 0x028f, 0x1bd4, 0x0088, PQI_HWIF_SRCV, "RT0804M7R"},
{0x9005, 0x028f, 0x1bd4, 0x0089, PQI_HWIF_SRCV, "RT0808M7R"},
{0x9005, 0x028f, 0x1ff9, 0x0051, PQI_HWIF_SRCV, "MT0804M6R"},
{0x9005, 0x028f, 0x1ff9, 0x0053, PQI_HWIF_SRCV, "MT0808M6R"},
{0x9005, 0x028f, 0x1ff9, 0x0088, PQI_HWIF_SRCV, "RT0804M7R"},
{0x9005, 0x028f, 0x1ff9, 0x0089, PQI_HWIF_SRCV, "RT0808M7R"},
{0x9005, 0x028f, 0x1f51, 0x1002, PQI_HWIF_SRCV, "SmartRAID P7604-8i"},
{0x9005, 0x028f, 0x1f51, 0x1004, PQI_HWIF_SRCV, "SmartRAID P7604-8e"},
{0x9005, 0x028f, 0x1f51, 0x100f, PQI_HWIF_SRCV, "SmartRAID P7604N-8i"},
{0x9005, 0x028f, 0x9005, 0x14a0, PQI_HWIF_SRCV, "SmartRAID 3254-8i"},
{0x9005, 0x028f, 0x9005, 0x14a1, PQI_HWIF_SRCV, "SmartRAID 3204-8i"},
{0x9005, 0x028f, 0x9005, 0x14a2, PQI_HWIF_SRCV, "SmartRAID 3252-8i"},
{0x9005, 0x028f, 0x9005, 0x14a4, PQI_HWIF_SRCV, "SmartRAID 3254-8i /e"},
{0x9005, 0x028f, 0x9005, 0x14a5, PQI_HWIF_SRCV, "SmartRAID 3252-8i /e"},
{0x9005, 0x028f, 0x9005, 0x14a6, PQI_HWIF_SRCV, "SmartRAID 3204-8i /e"},
{0x9005, 0x028f, 0x1d49, 0x0624, PQI_HWIF_SRCV, "9450-8i 4GB Flash"},
/* (MSCC PM8262 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x14c0, PQI_HWIF_SRCV, "SmartHBA 2200-16i"},
{0x9005, 0x028f, 0x9005, 0x14c1, PQI_HWIF_SRCV, "HBA 1200-16i"},
{0x9005, 0x028f, 0x9005, 0x14c3, PQI_HWIF_SRCV, "HBA 1200-16e"},
{0x9005, 0x028f, 0x9005, 0x14c4, PQI_HWIF_SRCV, "HBA 1200-8e"},
{0x9005, 0x028f, 0x1f51, 0x1005, PQI_HWIF_SRCV, "SmartHBA P6600-16i"},
{0x9005, 0x028f, 0x1f51, 0x1007, PQI_HWIF_SRCV, "SmartHBA P6600-8i8e"},
{0x9005, 0x028f, 0x1f51, 0x1009, PQI_HWIF_SRCV, "SmartHBA P6600-16e"},
{0x9005, 0x028f, 0x1cf2, 0x54dc, PQI_HWIF_SRCV, "ZTE SmartIOC2200 RM346-16i"},
{0x9005, 0x028f, 0x1cf2, 0x0806, PQI_HWIF_SRCV, "ZTE SmartIOC2200 RS346-16i"},
{0x9005, 0x028f, 0x1d49, 0x0223, PQI_HWIF_SRCV, "4450-16i HBA"},
{0x9005, 0x028f, 0x1d49, 0x0224, PQI_HWIF_SRCV, "4450-8e HBA"},
{0x9005, 0x028f, 0x1d49, 0x0225, PQI_HWIF_SRCV, "4450-16e HBA"},
{0x9005, 0x028f, 0x1d49, 0x0521, PQI_HWIF_SRCV, "5450-16i"},
{0x9005, 0x028f, 0x207d, 0x4084, PQI_HWIF_SRCV, "HRDT TrustHBA H4100-16i"},
{0x9005, 0x028f, 0x207d, 0x4094, PQI_HWIF_SRCV, "HRDT TrustHBA H4100-16e"},
/* (MSCC PM8264 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x14b0, PQI_HWIF_SRCV, "SmartRAID 3254-16i"},
{0x9005, 0x028f, 0x9005, 0x14b1, PQI_HWIF_SRCV, "SmartRAID 3258-16i"},
{0x9005, 0x028f, 0x1f51, 0x1006, PQI_HWIF_SRCV, "SmartRAID P7608-16i"},
{0x9005, 0x028f, 0x1f51, 0x1008, PQI_HWIF_SRCV, "SmartRAID P7608-8i8e"},
{0x9005, 0x028f, 0x1f51, 0x100a, PQI_HWIF_SRCV, "SmartRAID P7608-16e"},
{0x9005, 0x028f, 0x1cf2, 0x54da, PQI_HWIF_SRCV, "ZTE SmartROC3200 RM344-16i 4G"},
{0x9005, 0x028f, 0x1cf2, 0x54db, PQI_HWIF_SRCV, "ZTE SmartROC3200 RM345-16i 8G"},
{0x9005, 0x028f, 0x1cf2, 0x0804, PQI_HWIF_SRCV, "ZTE SmartROC3200 RS344-16i 4G"},
{0x9005, 0x028f, 0x1cf2, 0x0805, PQI_HWIF_SRCV, "ZTE SmartROC3200 RS345-16i 8G"},
{0x9005, 0x028f, 0x1f51, 0x100e, PQI_HWIF_SRCV, "SmartRAID P7604N-16i"},
{0x9005, 0x028f, 0x1d49, 0x0625, PQI_HWIF_SRCV, "9450-16i 4GB Flash"},
{0x9005, 0x028f, 0x1d49, 0x0626, PQI_HWIF_SRCV, "9450-16i 8GB Flash"},
/* (MSCC PM8265 16x12G based) */
{0x9005, 0x028f, 0x1590, 0x02dc, PQI_HWIF_SRCV, "SR416i-a Gen10+"},
{0x9005, 0x028f, 0x9005, 0x1470, PQI_HWIF_SRCV, "SmartRAID 3200"},
{0x9005, 0x028f, 0x9005, 0x1471, PQI_HWIF_SRCV, "SmartRAID 3254-16i /e"},
{0x9005, 0x028f, 0x9005, 0x1472, PQI_HWIF_SRCV, "SmartRAID 3258-16i /e"},
{0x9005, 0x028f, 0x9005, 0x1473, PQI_HWIF_SRCV, "SmartRAID 3284-16io /e/uC"},
{0x9005, 0x028f, 0x9005, 0x1474, PQI_HWIF_SRCV, "SmartRAID 3254-16io /e"},
{0x9005, 0x028f, 0x9005, 0x1475, PQI_HWIF_SRCV, "SmartRAID 3254-16e /e"},
/* (MSCC PM8266 16x12G based) */
{0x9005, 0x028f, 0x1014, 0x0718, PQI_HWIF_SRCV, "IBM 4-Port 24G SAS"},
{0x9005, 0x028f, 0x9005, 0x1490, PQI_HWIF_SRCV, "HBA 1200p Ultra"},
{0x9005, 0x028f, 0x9005, 0x1491, PQI_HWIF_SRCV, "SmartHBA 2200p Ultra"},
{0x9005, 0x028f, 0x9005, 0x1402, PQI_HWIF_SRCV, "HBA Ultra 1200P-16i"},
{0x9005, 0x028f, 0x9005, 0x1441, PQI_HWIF_SRCV, "HBA Ultra 1200P-32i"},
{0x9005, 0x028f, 0x1137, 0x0300, PQI_HWIF_SRCV, "Cisco 24G TriMode M1 HBA LFF 32D UCSC-HBAMP1LL32"},
/* (MSCC PM8268 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x14d0, PQI_HWIF_SRCV, "SmartRAID Ultra 3258P-16i"},
/* (MSCC PM8269 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1400, PQI_HWIF_SRCV, "SmartRAID Ultra 3258P-16i /e"},
{0x9005, 0x028f, 0x1ff9, 0x00a1, PQI_HWIF_SRCV, "RT1608M6R16i"},
/* (MSCC PM8270 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1410, PQI_HWIF_SRCV, "HBA Ultra 1200P-16e"},
{0x9005, 0x028f, 0x9005, 0x1411, PQI_HWIF_SRCV, "HBA 1200 Ultra"},
{0x9005, 0x028f, 0x9005, 0x1412, PQI_HWIF_SRCV, "SmartHBA 2200 Ultra"},
{0x9005, 0x028f, 0x9005, 0x1463, PQI_HWIF_SRCV, "SmartHBA 2200-8io /e"},
{0x9005, 0x028f, 0x9005, 0x14c2, PQI_HWIF_SRCV, "SmartHBA 2200-16io /e"},
{0x9005, 0x028f, 0x1337, 0x02fa, PQI_HWIF_SRCV, "Cisco 24G TriMode M1 HBA 16D UCSC-HBA-M1L16"},
/* (MSCC PM8271 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x14e0, PQI_HWIF_SRCV, "SmartIOC PM8271"},
/* (MSCC PM8272 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1420, PQI_HWIF_SRCV, "SmartRAID Ultra 3254-16e"},
{0x9005, 0x028f, 0x1d49, 0x0628, PQI_HWIF_SRCV, "9450-16e 4GB Flash"},
/* (MSCC PM8273 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1430, PQI_HWIF_SRCV, "SmartRAID Ultra 3254-16e /e"},
{0x9005, 0x028f, 0x1137, 0x02f9, PQI_HWIF_SRCV, "Cisco 24G TriMode M1 RAID 4GB FBWC 16D UCSC-RAID-M1L16"},
{0x9005, 0x028f, 0x1137, 0x02ff, PQI_HWIF_SRCV, "Cisco 24G TriMode M1 RAID 4GB FBWC 6D UCSX-RAID-M1L6"},
/* (MSCC PM8274 16x12G based) */
{0x9005, 0x028f, 0x1e93, 0x1000, PQI_HWIF_SRCV, "ByteHBA JGH43024-8"},
{0x9005, 0x028f, 0x1e93, 0x1001, PQI_HWIF_SRCV, "ByteHBA JGH43034-8"},
{0x9005, 0x028f, 0x1e93, 0x1005, PQI_HWIF_SRCV, "ByteHBA JGH43014-8"},
{0x9005, 0x028f, 0x1f51, 0x100B, PQI_HWIF_SRCV, "SmartHBA P6600-24i"},
/* (MSCC PM8275 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x14f0, PQI_HWIF_SRCV, "SmartIOC PM8275"},
/* (MSCC PM8276 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1480, PQI_HWIF_SRCV, "SmartRAID 3200 Ultra"},
{0x9005, 0x028f, 0x1e93, 0x1002, PQI_HWIF_SRCV, "ByteHBA JGH44014-8"},
/* (MSCC PM8277 16x12G based) */
{0x9005, 0x028f, 0x1137, 0x02f8, PQI_HWIF_SRCV, "Cisco 24G TriMode M1 RAID 4GB FBWC 32D UCSC-RAID-MP1L32"},
/* (MSCC PM8278 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1440, PQI_HWIF_SRCV, "SmartRAID Ultra 3258P-32i"},
{0x9005, 0x028f, 0x1d49, 0x0627, PQI_HWIF_SRCV, "9450-32i 8GB Flash"},
/* (MSCC PM8279 32x12G based) */
{0x9005, 0x028f, 0x9005, 0x1450, PQI_HWIF_SRCV, "SmartRAID Ultra 3258P-32i /e"},
{0x9005, 0x028f, 0x1590, 0x0294, PQI_HWIF_SRCV, "SR932i-p Gen10+"},
{0x9005, 0x028f, 0x1590, 0x0381, PQI_HWIF_SRCV, "SR932i-p Gen11"},
{0x9005, 0x028f, 0x1590, 0x0382, PQI_HWIF_SRCV, "SR308i-p Gen11"},
{0x9005, 0x028f, 0x1590, 0x0383, PQI_HWIF_SRCV, "SR308i-o Gen11"},
{0x9005, 0x028f, 0x1590, 0x02db, PQI_HWIF_SRCV, "SR416ie-m Gen11"},
{0x9005, 0x028f, 0x1590, 0x032e, PQI_HWIF_SRCV, "SR416i-o Gen11"},
{0x9005, 0x028f, 0x9005, 0x1452, PQI_HWIF_SRCV, "SmartRAID 3200p Ultra"},
{0x9005, 0x028f, 0x1137, 0x02fe, PQI_HWIF_SRCV, "Cisco 24G TriMode M1 RAID LFF 32D UCSC-RAIDMP1LL32"},
/* (MSCC HBA/SMARTHBA/CFF SmartRAID - Lenovo 8X12G 16X12G based) */
{0x9005, 0x028f, 0x1d49, 0x0220, PQI_HWIF_SRCV, "4350-8i SAS/SATA HBA"},
{0x9005, 0x028f, 0x1d49, 0x0221, PQI_HWIF_SRCV, "4350-16i SAS/SATA HBA"},
{0x9005, 0x028f, 0x1d49, 0x0520, PQI_HWIF_SRCV, "5350-8i"},
{0x9005, 0x028f, 0x1d49, 0x0522, PQI_HWIF_SRCV, "5350-8i INTR"},
{0x9005, 0x028f, 0x1d49, 0x0620, PQI_HWIF_SRCV, "9350-8i 2GB Flash"},
{0x9005, 0x028f, 0x1d49, 0x0621, PQI_HWIF_SRCV, "9350-8i 2GB Flash INTR"},
{0x9005, 0x028f, 0x1d49, 0x0622, PQI_HWIF_SRCV, "9350-16i 4GB Flash"},
{0x9005, 0x028f, 0x1d49, 0x0623, PQI_HWIF_SRCV, "9350-16i 4GB Flash INTR"},
{0, 0, 0, 0, 0, 0}
};
struct pqi_ident
pqi_family_identifiers[] = {
{0x9005, 0x028f, 0, 0, PQI_HWIF_SRCV, "Smart Array Storage Controller"},
{0, 0, 0, 0, 0, 0}
};

43
sys/dev/smartpqi/smartpqi_defines.h
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -927,7 +927,7 @@ typedef struct pqi_pci_info
typedef struct _driver_info
{
unsigned char major_version;
unsigned long minor_version;
unsigned char minor_version;
unsigned char release_version;
unsigned long build_revision;
unsigned long max_targets;
@ -938,9 +938,13 @@ typedef struct _driver_info
typedef uint8_t *passthru_buf_type_t;
#define PQISRC_DRIVER_MAJOR __FreeBSD__
#define PQISRC_DRIVER_MINOR 4410
#if __FreeBSD__ <= 14
#define PQISRC_DRIVER_MINOR 4660
#else
#define PQISRC_DRIVER_MINOR 0
#endif
#define PQISRC_DRIVER_RELEASE 0
#define PQISRC_DRIVER_REVISION 2005
#define PQISRC_DRIVER_REVISION 2002
#define STR(s) # s
#define PQISRC_VERSION(a, b, c, d) STR(a.b.c-d)
@ -1234,19 +1238,21 @@ typedef struct sema OS_SEMA_LOCK_T;
/* Debug facility */
#define PQISRC_FLAGS_MASK 0x0000ffff
#define PQISRC_FLAGS_INIT 0x00000001
#define PQISRC_FLAGS_INFO 0x00000002
#define PQISRC_FLAGS_FUNC 0x00000004
#define PQISRC_FLAGS_TRACEIO 0x00000008
#define PQISRC_FLAGS_DISC 0x00000010
#define PQISRC_FLAGS_WARN 0x00000020
#define PQISRC_FLAGS_ERROR 0x00000040
#define PQISRC_FLAGS_NOTE 0x00000080
#define PQISRC_FLAGS_MASK 0x0000000000ff
#define PQISRC_FLAGS_INIT 0x0001
#define PQISRC_FLAGS_INFO 0x0002
#define PQISRC_FLAGS_FUNC 0x0004
#define PQISRC_FLAGS_TRACEIO 0x0008
#define PQISRC_FLAGS_DISC 0x0010
#define PQISRC_FLAGS_WARN 0x0020
#define PQISRC_FLAGS_ERROR 0x0040
#define PQISRC_FLAGS_NOTE 0x0080
#define PQISRC_LOG_LEVEL (PQISRC_FLAGS_WARN | PQISRC_FLAGS_ERROR | PQISRC_FLAGS_NOTE)
#define PQISRC_LOG_LEVEL (PQISRC_FLAGS_WARN | PQISRC_FLAGS_ERROR)
static int logging_level = PQISRC_LOG_LEVEL;
extern unsigned long logging_level;
#define DBG_SET_LOGGING_LEVEL(value) logging_level = value & PQISRC_FLAGS_MASK
#define DBG_INIT(fmt,args...) \
do { \
@ -1276,13 +1282,6 @@ static int logging_level = PQISRC_LOG_LEVEL;
} \
}while(0);
#define DBG_TRACEIO(fmt,args...) \
do { \
if (logging_level & PQISRC_FLAGS_TRACEIO) { \
printf("[TRACEIO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
} \
}while(0);
#define DBG_WARN(fmt,args...) \
do { \
if (logging_level & PQISRC_FLAGS_WARN) { \

167
sys/dev/smartpqi/smartpqi_discovery.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -189,7 +189,7 @@ pqisrc_set_btl(pqi_scsi_dev_t *device, int bus, int target, int lun)
* devices and multi-lun devices */
boolean_t
pqisrc_add_softs_entry(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device,
uint8_t *scsi3addr)
uint8_t const *scsi3addr)
{
/* Add physical devices with targets that need
* targets */
@ -269,7 +269,7 @@ pqisrc_add_softs_entry(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device,
}
}
DBG_ERR("The device is not a physical, lun or ptraid device"
"B %d: T %d: L %d\n", device->bus, device->target,
"B%d:T%d:L%d\n", device->bus, device->target,
device->lun );
return false;
@ -283,7 +283,7 @@ add_device_to_dev_list:
softs->dev_list[j] = device;
break;
}
DBG_NOTE("Added device [%d of %d]: B %d: T %d: L %d\n",
DBG_NOTE("Added device [%d of %d]: B%d:T%d:L%d\n",
j, softs->num_devs, device->bus, device->target,
device->lun);
return true;
@ -307,7 +307,6 @@ pqisrc_find_btl_list_index(pqisrc_softstate_t *softs,
if(bus == softs->bus_id &&
target == temp_device->target &&
lun == temp_device->lun){
DBG_DISC("Returning device list index %d\n", index);
return index;
}
@ -322,7 +321,7 @@ pqisrc_find_btl_list_index(pqisrc_softstate_t *softs,
/* Return a given index for a specific device within the
* softs dev_list */
int
pqisrc_find_device_list_index(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
pqisrc_find_device_list_index(pqisrc_softstate_t *softs, pqi_scsi_dev_t const *device)
{
int index;
@ -346,7 +345,7 @@ pqisrc_find_device_list_index(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
/* Delete a given device from the softs dev_list*/
int
pqisrc_delete_softs_entry(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
pqisrc_delete_softs_entry(pqisrc_softstate_t *softs, pqi_scsi_dev_t const *device)
{
int index;
@ -354,8 +353,8 @@ pqisrc_delete_softs_entry(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
if (0 <= index && index < MAX_TARGET_BIT) {
softs->dev_list[index] = NULL;
softs->num_devs--;
DBG_NOTE("Removing device : B %d: T %d: L %d positioned at %d\n",
device->bus, device->target, device->lun, softs->num_devs);
DBG_NOTE("Removing device: B%d:T%d:L%d positioned at %d\n",
device->bus, device->target, device->lun, index);
return PQI_STATUS_SUCCESS;
}
if (index == INVALID_ELEM) {
@ -414,7 +413,7 @@ pqisrc_build_send_raid_request(pqisrc_softstate_t *softs, struct dma_mem device_
int ret = PQI_STATUS_SUCCESS;
ib_queue_t *ib_q = &softs->op_raid_ib_q[PQI_DEFAULT_IB_QUEUE];
ob_queue_t *ob_q = &softs->op_ob_q[PQI_DEFAULT_IB_QUEUE];
ob_queue_t const *ob_q = &softs->op_ob_q[PQI_DEFAULT_IB_QUEUE];
rcb_t *rcb = NULL;
@ -740,13 +739,13 @@ pqisrc_get_phys_log_device_list(pqisrc_softstate_t *softs,
ret = pqisrc_get_physical_logical_luns(softs, SA_REPORT_PHYS, physical_dev_list, phys_data_length);
if (ret) {
DBG_ERR("report physical LUNs failed");
DBG_ERR("report physical LUNs failed\n");
return ret;
}
ret = pqisrc_get_physical_logical_luns(softs, SA_REPORT_LOG, logical_dev_list, log_data_length);
if (ret) {
DBG_ERR("report logical LUNs failed");
DBG_ERR("report logical LUNs failed\n");
return ret;
}
@ -763,7 +762,7 @@ pqisrc_get_phys_log_device_list(pqisrc_softstate_t *softs,
ret = pqisrc_get_queue_lun_list(softs, PQI_LOG_EXT_QUEUE_ENABLE, queue_dev_list, queue_data_length);
if (ret) {
DBG_ERR("report logical LUNs failed");
DBG_ERR("report logical LUNs failed\n");
return ret;
}
@ -808,13 +807,13 @@ pqisrc_get_phys_log_device_list(pqisrc_softstate_t *softs,
}
inline boolean_t
pqisrc_is_external_raid_device(pqi_scsi_dev_t *device)
pqisrc_is_external_raid_device(pqi_scsi_dev_t const *device)
{
return device->is_external_raid_device;
}
static inline boolean_t
pqisrc_is_external_raid_addr(uint8_t *scsi3addr)
pqisrc_is_external_raid_addr(uint8_t const *scsi3addr)
{
return scsi3addr[2] != 0;
}
@ -940,12 +939,12 @@ out:
/* Validate the RAID map parameters */
static int
pqisrc_raid_map_validation(pqisrc_softstate_t *softs,
pqi_scsi_dev_t *device, pqisrc_raid_map_t *raid_map)
pqi_scsi_dev_t const *device, pqisrc_raid_map_t *raid_map)
{
char *error_msg;
uint32_t raidmap_size;
uint32_t r5or6_blocks_per_row;
/* unsigned phys_dev_num; */
/* unsigned phys_dev_num; */
DBG_FUNC("IN\n");
@ -1033,7 +1032,7 @@ pqisrc_get_device_raidmap(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
if (raidmap_reported_size <= raidmap_alloc_size)
break;
DBG_NOTE("Raid map is larger than 1024 entries, request once again");
DBG_NOTE("Raid map is larger than 1024 entries, request once again\n");
os_mem_free(softs, (char*)raid_map, raidmap_alloc_size);
raidmap_alloc_size = raidmap_reported_size;
@ -1331,7 +1330,7 @@ pqisrc_get_physical_device_info(pqisrc_softstate_t *softs,
/* Function used to find the entry of the device in a list */
static device_status_t
pqisrc_scsi_find_entry(pqisrc_softstate_t *softs,
pqi_scsi_dev_t *device_to_find, pqi_scsi_dev_t **same_device)
pqi_scsi_dev_t const *device_to_find, pqi_scsi_dev_t **same_device)
{
pqi_scsi_dev_t *device;
int i;
@ -1361,7 +1360,7 @@ pqisrc_scsi_find_entry(pqisrc_softstate_t *softs,
/* Update the newly added devices as existed device */
static void
pqisrc_exist_device_update(pqisrc_softstate_t *softs,
pqisrc_exist_device_update(pqisrc_softstate_t const *softs,
pqi_scsi_dev_t *device_exist, pqi_scsi_dev_t *new_device)
{
DBG_FUNC("IN\n");
@ -1395,15 +1394,13 @@ pqisrc_exist_device_update(pqisrc_softstate_t *softs,
device_exist->offload_config = new_device->offload_config;
device_exist->offload_enabled_pending =
new_device->offload_enabled_pending;
if (device_exist->offload_to_mirror)
os_mem_free(softs,
(int *) device_exist->offload_to_mirror,
sizeof(*(device_exist->offload_to_mirror)));
if (device_exist->offload_to_mirror) {
device_exist->temp_offload_to_mirror = device_exist->offload_to_mirror;
}
device_exist->offload_to_mirror = new_device->offload_to_mirror;
if (device_exist->raid_map)
os_mem_free(softs,
(char *)device_exist->raid_map,
sizeof(*device_exist->raid_map));
if (device_exist->raid_map) {
device_exist->temp_raid_map = device_exist->raid_map;
}
device_exist->raid_map = new_device->raid_map;
/* To prevent these from being freed later. */
new_device->raid_map = NULL;
@ -1416,7 +1413,7 @@ static int
pqisrc_add_device(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
{
DBG_FUNC("IN\n");
DBG_NOTE("vendor: %s model: %s bus:%d target:%d lun:%d is_physical_device:0x%x expose_device:0x%x volume_offline 0x%x volume_status 0x%x \n",
DBG_NOTE("vendor: %s model: %s B%d:T%d:L%d is_physical_device:0x%x expose_device:0x%x volume_offline 0x%x volume_status 0x%x \n",
device->vendor, device->model, device->bus, device->target, device->lun, device->is_physical_device, device->expose_device, device->volume_offline, device->volume_status);
device->invalid = false;
@ -1439,7 +1436,7 @@ void
pqisrc_remove_device(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
{
DBG_FUNC("IN\n");
DBG_NOTE("vendor: %s model: %s bus:%d target:%d lun:%d is_physical_device:0x%x expose_device:0x%x volume_offline 0x%x volume_status 0x%x \n",
DBG_NOTE("vendor: %s model: %s B%d:T%d:L%d is_physical_device:0x%x expose_device:0x%x volume_offline 0x%x volume_status 0x%x \n",
device->vendor, device->model, device->bus, device->target, device->lun, device->is_physical_device, device->expose_device, device->volume_offline, device->volume_status);
device->invalid = true;
if (device->expose_device == false) {
@ -1460,63 +1457,9 @@ pqisrc_remove_device(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
}
/*
* When exposing new device to OS fails then adjst list according to the
* mid scsi list
*/
static void
pqisrc_adjust_list(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
{
int i;
unsigned char addr1[8], addr2[8];
pqi_scsi_dev_t *temp_device;
DBG_FUNC("IN\n");
if (!device) {
DBG_ERR("softs = %p: device is NULL !!!\n", softs);
return;
}
OS_ACQUIRE_SPINLOCK(&softs->devlist_lock);
uint8_t *scsi3addr;
/*For external raid device, there can be multiple luns
*with same target. So while freeing external raid device,
*free target only after removing all luns with same target.*/
if (pqisrc_is_external_raid_device(device)) {
memcpy(addr1, device->scsi3addr, 8);
for(i = 0; i < PQI_MAX_DEVICES; i++) {
if(softs->dev_list[i] == NULL)
continue;
temp_device = softs->dev_list[i];
memcpy(addr2, temp_device->scsi3addr, 8);
if(memcmp(addr1, addr2, 8) == 0) {
continue;
}
if (addr1[2] == addr2[2]) {
break;
}
}
if(i == PQI_MAX_DEVICES) {
pqisrc_remove_target_bit(softs, device->target);
}
}
if(pqisrc_delete_softs_entry(softs, device) == PQI_STATUS_SUCCESS){
scsi3addr = device->scsi3addr;
if (!pqisrc_is_logical_device(device) && !MASKED_DEVICE(scsi3addr)){
DBG_NOTE("About to remove target bit %d \n", device->target);
pqisrc_remove_target_bit(softs, device->target);
}
}
OS_RELEASE_SPINLOCK(&softs->devlist_lock);
pqisrc_device_mem_free(softs, device);
DBG_FUNC("OUT\n");
}
/* Debug routine used to display the RAID volume status of the device */
static void
pqisrc_display_volume_status(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
pqisrc_display_volume_status(pqisrc_softstate_t *softs, pqi_scsi_dev_t const *device)
{
char *status;
@ -1590,7 +1533,7 @@ pqisrc_display_volume_status(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
break;
}
DBG_NOTE("scsi BTL %d:%d:%d %s\n",
DBG_NOTE("scsi B%d:T%d:L%d %s\n",
device->bus, device->target, device->lun, status);
DBG_FUNC("OUT\n");
}
@ -1635,7 +1578,7 @@ pqisrc_free_device(pqisrc_softstate_t * softs, pqi_scsi_dev_t *device)
/* Find the entry in device list for the freed device softs->dev_list[i]&
*make it NULL before freeing the device memory
*/
index = pqisrc_find_device_list_index(softs, device);
index = pqisrc_find_btl_list_index(softs, device->bus, device->target, device->lun);
OS_ACQUIRE_SPINLOCK(&softs->devlist_lock);
scsi3addr = device->scsi3addr;
@ -1669,13 +1612,14 @@ pqisrc_free_device(pqisrc_softstate_t * softs, pqi_scsi_dev_t *device)
softs->dev_list[index] = NULL;
if (device->expose_device == true){
pqisrc_delete_softs_entry(softs, device);
DBG_NOTE("Removed memory for device : B %d: T %d: L %d\n",
DBG_NOTE("Removed memory for device: B%d:T%d:L%d\n",
device->bus, device->target, device->lun);
OS_RELEASE_SPINLOCK(&softs->devlist_lock);
pqisrc_device_mem_free(softs, device);
} else {
OS_RELEASE_SPINLOCK(&softs->devlist_lock);
}
}
@ -1684,7 +1628,6 @@ static void
pqisrc_update_device_list(pqisrc_softstate_t *softs,
pqi_scsi_dev_t *new_device_list[], int num_new_devices)
{
int ret;
int i;
device_status_t dev_status;
pqi_scsi_dev_t *device;
@ -1755,8 +1698,7 @@ pqisrc_update_device_list(pqisrc_softstate_t *softs,
if(device == NULL)
continue;
if (device->device_gone) {
if(device->in_remove == true)
{
if(device->in_remove == true) {
continue;
}
device->in_remove = true;
@ -1794,7 +1736,7 @@ pqisrc_update_device_list(pqisrc_softstate_t *softs,
continue;
if (device->offload_enabled != device->offload_enabled_pending)
{
DBG_NOTE("[%d:%d:%d]Changing AIO to %d (was %d)\n",
DBG_NOTE("[B%d:T%d:L%d]Changing AIO to %d (was %d)\n",
device->bus, device->target, device->lun,
device->offload_enabled_pending,
device->offload_enabled);
@ -1831,24 +1773,14 @@ pqisrc_update_device_list(pqisrc_softstate_t *softs,
device->firmware_queue_depth_set == false)
device->queue_depth = PQI_LOGICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH;
if (device->scsi_rescan) {
os_rescan_target(softs, device);
}
}
softs->ld_rescan = false;
OS_RELEASE_SPINLOCK(&softs->devlist_lock);
for(i = 0; i < nadded; i++) {
device = added[i];
if (device->expose_device) {
ret = pqisrc_add_device(softs, device);
if (ret) {
DBG_WARN("scsi %d:%d:%d addition failed, device not added\n",
device->bus, device->target, device->lun);
pqisrc_adjust_list(softs, device);
continue;
}
pqisrc_add_device(softs, device);
}
pqisrc_display_device_info(softs, "added", device);
@ -1874,7 +1806,22 @@ pqisrc_update_device_list(pqisrc_softstate_t *softs,
DBG_DISC("Current device %d : B%d:T%d:L%d\n",
i, device->bus, device->target,
device->lun);
if (device->scsi_rescan) {
os_rescan_target(softs, device);
}
if (device->temp_offload_to_mirror) {
os_mem_free(softs,
(int *) device->temp_offload_to_mirror,
sizeof(*(device->temp_offload_to_mirror)));
}
if (device->temp_raid_map) {
os_mem_free(softs,
(int *) device->temp_raid_map,
sizeof(*(device->temp_raid_map)));
}
}
softs->ld_rescan = false;
free_and_out:
if (added)
@ -1928,6 +1875,8 @@ pqisrc_write_driver_version_to_host_wellness(pqisrc_softstate_t *softs)
}
host_wellness_driver_ver->driver_version[sizeof(host_wellness_driver_ver->driver_version) - 1] = '\0';
host_wellness_driver_ver->dont_write_tag[0] = 'D';
host_wellness_driver_ver->dont_write_tag[1] = 'W';
host_wellness_driver_ver->end_tag[0] = 'Z';
host_wellness_driver_ver->end_tag[1] = 'Z';
@ -1941,7 +1890,7 @@ pqisrc_write_driver_version_to_host_wellness(pqisrc_softstate_t *softs)
os_mem_free(softs, (char *)host_wellness_driver_ver, data_length);
DBG_FUNC("OUT");
DBG_FUNC("OUT\n");
return rval;
}
@ -1974,8 +1923,8 @@ pqisrc_write_current_time_to_host_wellness(pqisrc_softstate_t *softs)
host_wellness_time->start_tag[3] = '>';
host_wellness_time->time_tag[0] = 'T';
host_wellness_time->time_tag[1] = 'D';
host_wellness_time->time_length = LE_16(offsetof(struct bmic_host_wellness_time, time_length) -
offsetof(struct bmic_host_wellness_time, century));
host_wellness_time->time_length = LE_16(offsetof(struct bmic_host_wellness_time, dont_write_tag) -
offsetof(struct bmic_host_wellness_time, hour));
os_get_time(host_wellness_time);
@ -1994,12 +1943,12 @@ pqisrc_write_current_time_to_host_wellness(pqisrc_softstate_t *softs)
os_mem_free(softs, (char *)host_wellness_time, data_length);
DBG_FUNC("OUT");
DBG_FUNC("OUT\n");
return rval;
}
static void
pqisrc_get_device_vpd_info(pqisrc_softstate_t *softs,
bmic_ident_physdev_t *bmic_phy_info,pqi_scsi_dev_t *device)
bmic_ident_physdev_t const *bmic_phy_info,pqi_scsi_dev_t *device)
{
DBG_FUNC("IN\n");
memcpy(&device->wwid, &bmic_phy_info->padding[79], sizeof(device->wwid));
@ -2102,7 +2051,7 @@ pqisrc_scan_devices(pqisrc_softstate_t *softs)
scsi3addr = lun_ext_entry->lunid;
/* Save the target sas adderess for external raid device */
/* Save the target sas address for external raid device */
if(lun_ext_entry->device_type == CONTROLLER_DEVICE) {
#ifdef PQI_NEED_RESCAN_TIMER_FOR_RBOD_HOTPLUG
num_ext_raid_devices++;

10
sys/dev/smartpqi/smartpqi_event.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -59,7 +59,7 @@ pqisrc_wait_for_rescan_complete(pqisrc_softstate_t *softs)
*/
static void
pqisrc_acknowledge_event(pqisrc_softstate_t *softs,
struct pqi_event *event)
struct pqi_event const *event)
{
int ret;
@ -225,7 +225,7 @@ pqisrc_process_event_intr_src(pqisrc_softstate_t *softs,int obq_id)
os_eventtaskqueue_enqueue(softs);
}
DBG_FUNC("OUT");
DBG_FUNC("OUT\n");
return PQI_STATUS_SUCCESS;
@ -241,7 +241,7 @@ pqisrc_build_send_vendor_request(pqisrc_softstate_t *softs,
{
int ret = PQI_STATUS_SUCCESS;
ib_queue_t *op_ib_q = &softs->op_raid_ib_q[PQI_DEFAULT_IB_QUEUE];
ob_queue_t *ob_q = &softs->op_ob_q[PQI_DEFAULT_IB_QUEUE];
ob_queue_t const *ob_q = &softs->op_ob_q[PQI_DEFAULT_IB_QUEUE];
rcb_t *rcb = NULL;
@ -341,7 +341,7 @@ err_out:
static int
pqi_event_configure(pqisrc_softstate_t *softs ,
pqi_event_config_request_t *request,
dma_mem_t *buff)
dma_mem_t const *buff)
{
int ret = PQI_STATUS_SUCCESS;

32
sys/dev/smartpqi/smartpqi_helper.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -30,7 +30,7 @@
* Function used to validate the adapter health.
*/
boolean_t
pqisrc_ctrl_offline(pqisrc_softstate_t *softs)
pqisrc_ctrl_offline(pqisrc_softstate_t const *softs)
{
DBG_FUNC("IN\n");
@ -83,12 +83,10 @@ pqisrc_take_ctrl_offline(pqisrc_softstate_t *softs)
{
DBG_FUNC("IN\n");
int lockupcode = 0;
softs->ctrl_online = false;
if (SIS_IS_KERNEL_PANIC(softs)) {
lockupcode = PCI_MEM_GET32(softs, &softs->ioa_reg->mb[7], LEGACY_SIS_SRCV_OFFSET_MAILBOX_7);
int lockupcode = PCI_MEM_GET32(softs, &softs->ioa_reg->mb[7], LEGACY_SIS_SRCV_OFFSET_MAILBOX_7);
DBG_ERR("Controller FW is not running, Lockup code = %x\n", lockupcode);
}
else {
@ -172,7 +170,7 @@ pqisrc_wait_on_condition(pqisrc_softstate_t *softs, rcb_t *rcb,
}
if (pqisrc_ctrl_offline(softs)) {
DBG_ERR("Controller is Offline");
DBG_ERR("Controller is Offline\n");
ret = PQI_STATUS_FAILURE;
break;
}
@ -187,29 +185,29 @@ pqisrc_wait_on_condition(pqisrc_softstate_t *softs, rcb_t *rcb,
/* Function used to validate the device wwid. */
boolean_t
pqisrc_device_equal(pqi_scsi_dev_t *dev1,
pqi_scsi_dev_t *dev2)
pqisrc_device_equal(pqi_scsi_dev_t const *dev1,
pqi_scsi_dev_t const *dev2)
{
return dev1->wwid == dev2->wwid;
}
/* Function used to validate the device scsi3addr. */
boolean_t
pqisrc_scsi3addr_equal(uint8_t *scsi3addr1, uint8_t *scsi3addr2)
pqisrc_scsi3addr_equal(uint8_t const *scsi3addr1, uint8_t const *scsi3addr2)
{
return memcmp(scsi3addr1, scsi3addr2, 8) == 0;
}
/* Function used to validate hba_lunid */
boolean_t
pqisrc_is_hba_lunid(uint8_t *scsi3addr)
pqisrc_is_hba_lunid(uint8_t const *scsi3addr)
{
return pqisrc_scsi3addr_equal(scsi3addr, RAID_CTLR_LUNID);
}
/* Function used to validate type of device */
boolean_t
pqisrc_is_logical_device(pqi_scsi_dev_t *device)
pqisrc_is_logical_device(pqi_scsi_dev_t const *device)
{
return !device->is_physical_device;
}
@ -256,10 +254,10 @@ pqisrc_raidlevel_to_string(uint8_t raid_level)
/* Debug routine for displaying device info */
void pqisrc_display_device_info(pqisrc_softstate_t *softs,
char *action, pqi_scsi_dev_t *device)
char const *action, pqi_scsi_dev_t *device)
{
if (device->is_physical_device) {
DBG_NOTE("%s scsi BTL %d:%d:%d: %.8s %.16s %-12s "
DBG_NOTE("%s scsi B%d:T%d:L%d %.8s %.16s %-12s "
"SSDSmartPathCap%c En%c Exp%c qd=%d\n",
action,
device->bus,
@ -273,7 +271,7 @@ void pqisrc_display_device_info(pqisrc_softstate_t *softs,
device->expose_device ? '+' : '-',
device->queue_depth);
} else if (device->devtype == RAID_DEVICE) {
DBG_NOTE("%s scsi BTL %d:%d:%d: %.8s %.16s %-12s "
DBG_NOTE("%s scsi B%d:T%d:L%d %.8s %.16s %-12s "
"SSDSmartPathCap%c En%c Exp%c qd=%d\n",
action,
device->bus,
@ -287,7 +285,7 @@ void pqisrc_display_device_info(pqisrc_softstate_t *softs,
device->expose_device ? '+' : '-',
device->queue_depth);
} else if (device->devtype == CONTROLLER_DEVICE) {
DBG_NOTE("%s scsi BTL %d:%d:%d: %.8s %.16s %-12s "
DBG_NOTE("%s scsi B%d:T%d:L%d %.8s %.16s %-12s "
"SSDSmartPathCap%c En%c Exp%c qd=%d\n",
action,
device->bus,
@ -301,7 +299,7 @@ void pqisrc_display_device_info(pqisrc_softstate_t *softs,
device->expose_device ? '+' : '-',
device->queue_depth);
} else {
DBG_NOTE("%s scsi BTL %d:%d:%d: %.8s %.16s %-12s "
DBG_NOTE("%s scsi B%d:T%d:L%d %.8s %.16s %-12s "
"SSDSmartPathCap%c En%c Exp%c qd=%d devtype=%d\n",
action,
device->bus,
@ -335,7 +333,7 @@ check_struct_sizes(void)
64 bit and 32 bit system*/
ASSERT(sizeof(IOCTL_Command_struct)== 86 ||
sizeof(IOCTL_Command_struct)== 82);
ASSERT(sizeof(struct bmic_host_wellness_driver_version)== 42);
ASSERT(sizeof(struct bmic_host_wellness_driver_version)== 44);
ASSERT(sizeof(struct bmic_host_wellness_time)== 20);
ASSERT(sizeof(struct pqi_dev_adminq_cap)== 8);
ASSERT(sizeof(struct admin_q_param)== 4);

13
sys/dev/smartpqi/smartpqi_init.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -234,7 +234,7 @@ pqisrc_decide_opq_config(pqisrc_softstate_t *softs)
DBG_FUNC("IN\n");
DBG_INIT("softs->intr_count : %d softs->num_cpus_online : %d",
DBG_INIT("softs->intr_count : %d softs->num_cpus_online : %d\n",
softs->intr_count, softs->num_cpus_online);
/* TODO : Get the number of IB and OB queues from OS layer */
@ -437,7 +437,6 @@ int
pqi_reset(pqisrc_softstate_t *softs)
{
int ret = PQI_STATUS_SUCCESS;
uint32_t val = 0;
pqi_reset_reg_t pqi_reset_reg;
DBG_FUNC("IN\n");
@ -445,7 +444,7 @@ pqi_reset(pqisrc_softstate_t *softs)
if (true == softs->ctrl_in_pqi_mode) {
if (softs->pqi_reset_quiesce_allowed) {
val = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
int val = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
LEGACY_SIS_IDBR);
val |= SIS_PQI_RESET_QUIESCE;
PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
@ -629,7 +628,7 @@ pqisrc_wait_for_cmnd_complete(pqisrc_softstate_t *softs)
int count = 0;
int ret = PQI_STATUS_SUCCESS;
DBG_NOTE("softs->taglist.num_elem : %u",softs->taglist.num_elem);
DBG_NOTE("softs->taglist.num_elem : %u\n",softs->taglist.num_elem);
if (softs->taglist.num_elem == softs->max_outstanding_io)
return ret;
@ -650,7 +649,7 @@ pqisrc_wait_for_cmnd_complete(pqisrc_softstate_t *softs)
OS_SLEEP(1000);
count++;
if(count % 1000 == 0) {
DBG_WARN("Waited for %d seconds", count/1000);
DBG_WARN("Waited for %d seconds\n", count/1000);
}
if (count >= PQI_QUIESCE_TIMEOUT) {
return PQI_STATUS_FAILURE;
@ -849,7 +848,7 @@ pqisrc_init(pqisrc_softstate_t *softs)
/* update driver version in to FW */
ret = pqisrc_write_driver_version_to_host_wellness(softs);
if (ret) {
DBG_ERR(" Failed to update driver version in to FW");
DBG_ERR(" Failed to update driver version in to FW\n");
goto err_host_wellness;
}

3
sys/dev/smartpqi/smartpqi_intr.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -35,7 +35,6 @@ os_get_processor_config(pqisrc_softstate_t *softs)
{
DBG_FUNC("IN\n");
softs->num_cpus_online = mp_ncpus;
bsd_set_hint_adapter_cpu_config(softs);
DBG_FUNC("OUT\n");
return PQI_STATUS_SUCCESS;

12
sys/dev/smartpqi/smartpqi_ioctl.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -74,7 +74,7 @@ smartpqi_close(struct cdev *cdev, int flags, int devtype,
* ioctl for getting driver info
*/
static void
smartpqi_get_driver_info_ioctl(caddr_t udata, struct cdev *cdev)
smartpqi_get_driver_info_ioctl(caddr_t udata, struct cdev const *cdev)
{
struct pqisrc_softstate *softs = cdev->si_drv1;
pdriver_info driver_info = (pdriver_info)udata;
@ -82,7 +82,11 @@ smartpqi_get_driver_info_ioctl(caddr_t udata, struct cdev *cdev)
DBG_FUNC("IN udata = %p cdev = %p\n", udata, cdev);
driver_info->major_version = PQISRC_DRIVER_MAJOR;
#if __FreeBSD__ <= 14
driver_info->minor_version = (unsigned char) ((PQISRC_DRIVER_MINOR >> 4) & 0xFF);
#else
driver_info->minor_version = PQISRC_DRIVER_MINOR;
#endif
driver_info->release_version = PQISRC_DRIVER_RELEASE;
driver_info->build_revision = PQISRC_DRIVER_REVISION;
driver_info->max_targets = PQI_MAX_DEVICES - 1;
@ -96,7 +100,7 @@ smartpqi_get_driver_info_ioctl(caddr_t udata, struct cdev *cdev)
* ioctl for getting controller info
*/
static void
smartpqi_get_pci_info_ioctl(caddr_t udata, struct cdev *cdev)
smartpqi_get_pci_info_ioctl(caddr_t udata, struct cdev const *cdev)
{
struct pqisrc_softstate *softs = cdev->si_drv1;
device_t dev = softs->os_specific.pqi_dev;
@ -242,7 +246,7 @@ pqisrc_passthru_ioctl(struct pqisrc_softstate *softs, void *arg, int mode)
pqisrc_raid_req_t request;
raid_path_error_info_elem_t error_info;
ib_queue_t *ib_q = &softs->op_raid_ib_q[PQI_DEFAULT_IB_QUEUE];
ob_queue_t *ob_q = &softs->op_ob_q[PQI_DEFAULT_IB_QUEUE];
ob_queue_t const *ob_q = &softs->op_ob_q[PQI_DEFAULT_IB_QUEUE];
rcb_t *rcb = NULL;
memset(&request, 0, sizeof(request));

320
sys/dev/smartpqi/smartpqi_main.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -29,290 +29,14 @@
*/
#include "smartpqi_includes.h"
#include "smartpqi_controllers.h"
CTASSERT(BSD_SUCCESS == PQI_STATUS_SUCCESS);
/*
* Supported devices
*/
struct pqi_ident
{
u_int16_t vendor;
u_int16_t device;
u_int16_t subvendor;
u_int16_t subdevice;
int hwif;
char *desc;
} pqi_identifiers[] = {
/* (MSCC PM8205 8x12G based) */
{0x9005, 0x028f, 0x103c, 0x600, PQI_HWIF_SRCV, "P408i-p SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x601, PQI_HWIF_SRCV, "P408e-p SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x602, PQI_HWIF_SRCV, "P408i-a SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x603, PQI_HWIF_SRCV, "P408i-c SR Gen10"},
{0x9005, 0x028f, 0x1028, 0x1FE0, PQI_HWIF_SRCV, "SmartRAID 3162-8i/eDell"},
{0x9005, 0x028f, 0x9005, 0x608, PQI_HWIF_SRCV, "SmartRAID 3162-8i/e"},
{0x9005, 0x028f, 0x103c, 0x609, PQI_HWIF_SRCV, "P408i-sb SR G10"},
/* (MSCC PM8225 8x12G based) */
{0x9005, 0x028f, 0x103c, 0x650, PQI_HWIF_SRCV, "E208i-p SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x651, PQI_HWIF_SRCV, "E208e-p SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x652, PQI_HWIF_SRCV, "E208i-c SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x654, PQI_HWIF_SRCV, "E208i-a SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x655, PQI_HWIF_SRCV, "P408e-m SR Gen10"},
{0x9005, 0x028f, 0x9005, 0x659, PQI_HWIF_SRCV, "2100C8iOXS"},
/* (MSCC PM8221 8x12G based) */
{0x9005, 0x028f, 0x103c, 0x700, PQI_HWIF_SRCV, "P204i-c SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x701, PQI_HWIF_SRCV, "P204i-b SR Gen10"},
{0x9005, 0x028f, 0x193d, 0x1104, PQI_HWIF_SRCV, "UN RAID P2404-Mf-4i-2GB"},
{0x9005, 0x028f, 0x193d, 0x1106, PQI_HWIF_SRCV, "UN RAID P2404-Mf-4i-1GB"},
{0x9005, 0x028f, 0x193d, 0x1108, PQI_HWIF_SRCV, "UN RAID P4408-Ma-8i-2GB"},
{0x9005, 0x028f, 0x193d, 0x1109, PQI_HWIF_SRCV, "UN RAID P4408-Mr-8i-2GB"},
/* (MSCC PM8204 8x12G based) */
{0x9005, 0x028f, 0x9005, 0x800, PQI_HWIF_SRCV, "SmartRAID 3154-8i"},
{0x9005, 0x028f, 0x9005, 0x801, PQI_HWIF_SRCV, "SmartRAID 3152-8i"},
{0x9005, 0x028f, 0x9005, 0x802, PQI_HWIF_SRCV, "SmartRAID 3151-4i"},
{0x9005, 0x028f, 0x9005, 0x803, PQI_HWIF_SRCV, "SmartRAID 3101-4i"},
{0x9005, 0x028f, 0x9005, 0x804, PQI_HWIF_SRCV, "SmartRAID 3154-8e"},
{0x9005, 0x028f, 0x9005, 0x805, PQI_HWIF_SRCV, "SmartRAID 3102-8i"},
{0x9005, 0x028f, 0x9005, 0x806, PQI_HWIF_SRCV, "SmartRAID 3100"},
{0x9005, 0x028f, 0x9005, 0x807, PQI_HWIF_SRCV, "SmartRAID 3162-8i"},
{0x9005, 0x028f, 0x152d, 0x8a22, PQI_HWIF_SRCV, "QS-8204-8i"},
{0x9005, 0x028f, 0x193d, 0xf460, PQI_HWIF_SRCV, "UN RAID P460-M4"},
{0x9005, 0x028f, 0x193d, 0xf461, PQI_HWIF_SRCV, "UN RAID P460-B4"},
{0x9005, 0x028f, 0x1bd4, 0x004b, PQI_HWIF_SRCV, "PM8204-2GB"},
{0x9005, 0x028f, 0x1bd4, 0x004c, PQI_HWIF_SRCV, "PM8204-4GB"},
{0x9005, 0x028f, 0x193d, 0x1105, PQI_HWIF_SRCV, "UN RAID P4408-Mf-8i-2GB"},
{0x9005, 0x028f, 0x193d, 0x1107, PQI_HWIF_SRCV, "UN RAID P4408-Mf-8i-4GB"},
{0x9005, 0x028f, 0x1d8d, 0x800, PQI_HWIF_SRCV, "Fiberhome SmartRAID AIS-8204-8i"},
{0x9005, 0x028f, 0x9005, 0x0808, PQI_HWIF_SRCV, "SmartRAID 3101E-4i"},
{0x9005, 0x028f, 0x9005, 0x0809, PQI_HWIF_SRCV, "SmartRAID 3102E-8i"},
{0x9005, 0x028f, 0x9005, 0x080a, PQI_HWIF_SRCV, "SmartRAID 3152-8i/N"},
{0x9005, 0x028f, 0x1cc4, 0x0101, PQI_HWIF_SRCV, "Ramaxel FBGF-RAD PM8204"},
/* (MSCC PM8222 8x12G based) */
{0x9005, 0x028f, 0x9005, 0x900, PQI_HWIF_SRCV, "SmartHBA 2100-8i"},
{0x9005, 0x028f, 0x9005, 0x901, PQI_HWIF_SRCV, "SmartHBA 2100-4i"},
{0x9005, 0x028f, 0x9005, 0x902, PQI_HWIF_SRCV, "HBA 1100-8i"},
{0x9005, 0x028f, 0x9005, 0x903, PQI_HWIF_SRCV, "HBA 1100-4i"},
{0x9005, 0x028f, 0x9005, 0x904, PQI_HWIF_SRCV, "SmartHBA 2100-8e"},
{0x9005, 0x028f, 0x9005, 0x905, PQI_HWIF_SRCV, "HBA 1100-8e"},
{0x9005, 0x028f, 0x9005, 0x906, PQI_HWIF_SRCV, "SmartHBA 2100-4i4e"},
{0x9005, 0x028f, 0x9005, 0x907, PQI_HWIF_SRCV, "HBA 1100"},
{0x9005, 0x028f, 0x9005, 0x908, PQI_HWIF_SRCV, "SmartHBA 2100"},
{0x9005, 0x028f, 0x9005, 0x90a, PQI_HWIF_SRCV, "SmartHBA 2100A-8i"},
{0x9005, 0x028f, 0x193d, 0x8460, PQI_HWIF_SRCV, "UN HBA H460-M1"},
{0x9005, 0x028f, 0x193d, 0x8461, PQI_HWIF_SRCV, "UN HBA H460-B1"},
{0x9005, 0x028f, 0x193d, 0xc460, PQI_HWIF_SRCV, "UN RAID P460-M2"},
{0x9005, 0x028f, 0x193d, 0xc461, PQI_HWIF_SRCV, "UN RAID P460-B2"},
{0x9005, 0x028f, 0x1bd4, 0x004a, PQI_HWIF_SRCV, "PM8222-SHBA"},
{0x9005, 0x028f, 0x13fe, 0x8312, PQI_HWIF_SRCV, "MIC-8312BridgeB"},
{0x9005, 0x028f, 0x1bd4, 0x004f, PQI_HWIF_SRCV, "PM8222-HBA"},
{0x9005, 0x028f, 0x1d8d, 0x908, PQI_HWIF_SRCV, "Fiberhome SmartHBA AIS-8222-8i"},
{0x9005, 0x028f, 0x1bd4, 0x006C, PQI_HWIF_SRCV, "RS0800M5E8i"},
{0x9005, 0x028f, 0x1bd4, 0x006D, PQI_HWIF_SRCV, "RS0800M5H8i"},
{0x9005, 0x028f, 0x1cc4, 0x0201, PQI_HWIF_SRCV, "Ramaxel FBGF-RAD PM8222"},
/* (SRCx MSCC FVB 24x12G based) */
{0x9005, 0x028f, 0x103c, 0x1001, PQI_HWIF_SRCV, "MSCC FVB"},
/* (MSCC PM8241 24x12G based) */
/* (MSCC PM8242 24x12G based) */
{0x9005, 0x028f, 0x152d, 0x8a37, PQI_HWIF_SRCV, "QS-8242-24i"},
{0x9005, 0x028f, 0x9005, 0x1300, PQI_HWIF_SRCV, "HBA 1100-8i8e"},
{0x9005, 0x028f, 0x9005, 0x1301, PQI_HWIF_SRCV, "HBA 1100-24i"},
{0x9005, 0x028f, 0x9005, 0x1302, PQI_HWIF_SRCV, "SmartHBA 2100-8i8e"},
{0x9005, 0x028f, 0x9005, 0x1303, PQI_HWIF_SRCV, "SmartHBA 2100-24i"},
{0x9005, 0x028f, 0x105b, 0x1321, PQI_HWIF_SRCV, "8242-24i"},
{0x9005, 0x028f, 0x1bd4, 0x0045, PQI_HWIF_SRCV, "SMART-HBA 8242-24i"},
{0x9005, 0x028f, 0x1bd4, 0x006B, PQI_HWIF_SRCV, "RS0800M5H24i"},
{0x9005, 0x028f, 0x1bd4, 0x0070, PQI_HWIF_SRCV, "RS0800M5E24i"},
/* (MSCC PM8236 16x12G based) */
{0x9005, 0x028f, 0x152d, 0x8a24, PQI_HWIF_SRCV, "QS-8236-16i"},
{0x9005, 0x028f, 0x9005, 0x1380, PQI_HWIF_SRCV, "SmartRAID 3154-16i"},
{0x9005, 0x028f, 0x1bd4, 0x0046, PQI_HWIF_SRCV, "RAID 8236-16i"},
{0x9005, 0x028f, 0x1d8d, 0x806, PQI_HWIF_SRCV, "Fiberhome SmartRAID AIS-8236-16i"},
{0x9005, 0x028f, 0x1cf2, 0x0B27, PQI_HWIF_SRCV, "ZTE SmartROC3100 SDPSA/B-18i 4G"},
{0x9005, 0x028f, 0x1cf2, 0x0B45, PQI_HWIF_SRCV, "ZTE SmartROC3100 SDPSA/B_L-18i 2G"},
{0x9005, 0x028f, 0x1cf2, 0x5445, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM241-18i 2G"},
{0x9005, 0x028f, 0x1cf2, 0x5446, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM242-18i 4G"},
{0x9005, 0x028f, 0x1cf2, 0x5449, PQI_HWIF_SRCV, "ZTE SmartROC3100 RS241-18i 2G"},
{0x9005, 0x028f, 0x1cf2, 0x544A, PQI_HWIF_SRCV, "ZTE SmartROC3100 RS242-18i 4G"},
{0x9005, 0x028f, 0x1cf2, 0x544D, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM241B-18i 2G"},
{0x9005, 0x028f, 0x1cf2, 0x544E, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM242B-18i 4G"},
{0x9005, 0x028f, 0x1bd4, 0x006F, PQI_HWIF_SRCV, "RS0804M5R16i"},
/* (MSCC PM8237 24x12G based) */
{0x9005, 0x028f, 0x103c, 0x1100, PQI_HWIF_SRCV, "P816i-a SR Gen10"},
{0x9005, 0x028f, 0x103c, 0x1101, PQI_HWIF_SRCV, "P416ie-m SR G10"},
/* (MSCC PM8238 16x12G based) */
{0x9005, 0x028f, 0x152d, 0x8a23, PQI_HWIF_SRCV, "QS-8238-16i"},
{0x9005, 0x028f, 0x9005, 0x1280, PQI_HWIF_SRCV, "HBA 1100-16i"},
{0x9005, 0x028f, 0x9005, 0x1281, PQI_HWIF_SRCV, "HBA 1100-16e"},
{0x9005, 0x028f, 0x105b, 0x1211, PQI_HWIF_SRCV, "8238-16i"},
{0x9005, 0x028f, 0x1bd4, 0x0048, PQI_HWIF_SRCV, "SMART-HBA 8238-16i"},
{0x9005, 0x028f, 0x9005, 0x1282, PQI_HWIF_SRCV, "SmartHBA 2100-16i"},
{0x9005, 0x028f, 0x1d8d, 0x916, PQI_HWIF_SRCV, "Fiberhome SmartHBA AIS-8238-16i"},
{0x9005, 0x028f, 0x1458, 0x1000, PQI_HWIF_SRCV, "GIGABYTE SmartHBA CLN1832"},
{0x9005, 0x028f, 0x1cf2, 0x0B29, PQI_HWIF_SRCV, "ZTE SmartIOC2100 SDPSA/B_I-18i"},
{0x9005, 0x028f, 0x1cf2, 0x5447, PQI_HWIF_SRCV, "ZTE SmartIOC2100 RM243-18i"},
{0x9005, 0x028f, 0x1cf2, 0x544B, PQI_HWIF_SRCV, "ZTE SmartIOC2100 RS243-18i"},
{0x9005, 0x028f, 0x1cf2, 0x544F, PQI_HWIF_SRCV, "ZTE SmartIOC2100 RM243B-18i"},
{0x9005, 0x028f, 0x1bd4, 0x0071, PQI_HWIF_SRCV, "RS0800M5H16i"},
{0x9005, 0x028f, 0x1bd4, 0x0072, PQI_HWIF_SRCV, "RS0800M5E16i"},
/* (MSCC PM8240 24x12G based) */
{0x9005, 0x028f, 0x152d, 0x8a36, PQI_HWIF_SRCV, "QS-8240-24i"},
{0x9005, 0x028f, 0x9005, 0x1200, PQI_HWIF_SRCV, "SmartRAID 3154-24i"},
{0x9005, 0x028f, 0x9005, 0x1201, PQI_HWIF_SRCV, "SmartRAID 3154-8i16e"},
{0x9005, 0x028f, 0x9005, 0x1202, PQI_HWIF_SRCV, "SmartRAID 3154-8i8e"},
{0x9005, 0x028f, 0x1bd4, 0x0047, PQI_HWIF_SRCV, "RAID 8240-24i"},
{0x9005, 0x028f, 0x1dfc, 0x3161, PQI_HWIF_SRCV, "NTCOM SAS3 RAID-24i"},
{0x9005, 0x028f, 0x1F0C, 0x3161, PQI_HWIF_SRCV, "NT RAID 3100-24i"},
/* Huawei ID's */
{0x9005, 0x028f, 0x19e5, 0xd227, PQI_HWIF_SRCV, "SR465C-M 4G"},
{0x9005, 0x028f, 0x19e5, 0xd22a, PQI_HWIF_SRCV, "SR765-M"},
{0x9005, 0x028f, 0x19e5, 0xd228, PQI_HWIF_SRCV, "SR455C-M 2G"},
{0x9005, 0x028f, 0x19e5, 0xd22c, PQI_HWIF_SRCV, "SR455C-M 4G"},
{0x9005, 0x028f, 0x19e5, 0xd229, PQI_HWIF_SRCV, "SR155-M"},
{0x9005, 0x028f, 0x19e5, 0xd22b, PQI_HWIF_SRCV, "SR455C-ME 4G"},
/* (MSCC PM8252 8x12G based) */
{0x9005, 0x028f, 0x193d, 0x110b, PQI_HWIF_SRCV, "UN HBA H4508-Mf-8i"},
{0x9005, 0x028f, 0x1bd4, 0x0052, PQI_HWIF_SRCV, "MT0801M6E"},
{0x9005, 0x028f, 0x1bd4, 0x0054, PQI_HWIF_SRCV, "MT0800M6H"},
{0x9005, 0x028f, 0x1bd4, 0x0086, PQI_HWIF_SRCV, "RT0800M7E"},
{0x9005, 0x028f, 0x1bd4, 0x0087, PQI_HWIF_SRCV, "RT0800M7H"},
{0x9005, 0x028f, 0x1f51, 0x1001, PQI_HWIF_SRCV, "SmartHBA P6600-8i"},
{0x9005, 0x028f, 0x1f51, 0x1003, PQI_HWIF_SRCV, "SmartHBA P6600-8e"},
{0x9005, 0x028f, 0x9005, 0x1460, PQI_HWIF_SRCV, "HBA 1200"},
{0x9005, 0x028f, 0x9005, 0x1461, PQI_HWIF_SRCV, "SmartHBA 2200"},
{0x9005, 0x028f, 0x9005, 0x1462, PQI_HWIF_SRCV, "HBA 1200-8i"},
/* (MSCC PM8254 32x12G based) */
{0x9005, 0x028f, 0x1bd4, 0x0051, PQI_HWIF_SRCV, "MT0804M6R"},
{0x9005, 0x028f, 0x1bd4, 0x0053, PQI_HWIF_SRCV, "MT0808M6R"},
{0x9005, 0x028f, 0x1bd4, 0x0088, PQI_HWIF_SRCV, "RT0804M7R"},
{0x9005, 0x028f, 0x1bd4, 0x0089, PQI_HWIF_SRCV, "RT0808M7R"},
{0x9005, 0x028f, 0x1f51, 0x1002, PQI_HWIF_SRCV, "SmartRAID P7604-8i"},
{0x9005, 0x028f, 0x1f51, 0x1004, PQI_HWIF_SRCV, "SmartRAID P7604-8e"},
{0x9005, 0x028f, 0x9005, 0x14a0, PQI_HWIF_SRCV, "SmartRAID 3254-8i"},
{0x9005, 0x028f, 0x9005, 0x14a1, PQI_HWIF_SRCV, "SmartRAID 3204-8i"},
{0x9005, 0x028f, 0x9005, 0x14a2, PQI_HWIF_SRCV, "SmartRAID 3252-8i"},
{0x9005, 0x028f, 0x9005, 0x14a4, PQI_HWIF_SRCV, "SmartRAID 3254-8i /e"},
{0x9005, 0x028f, 0x9005, 0x14a5, PQI_HWIF_SRCV, "SmartRAID 3252-8i /e"},
{0x9005, 0x028f, 0x9005, 0x14a6, PQI_HWIF_SRCV, "SmartRAID 3204-8i /e"},
/* (MSCC PM8262 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x14c0, PQI_HWIF_SRCV, "SmartHBA 2200-16i"},
{0x9005, 0x028f, 0x9005, 0x14c1, PQI_HWIF_SRCV, "HBA 1200-16i"},
{0x9005, 0x028f, 0x9005, 0x14c3, PQI_HWIF_SRCV, "HBA 1200-16e"},
{0x9005, 0x028f, 0x9005, 0x14c4, PQI_HWIF_SRCV, "HBA 1200-8e"},
{0x9005, 0x028f, 0x1f51, 0x1005, PQI_HWIF_SRCV, "SmartHBA P6600-16i"},
{0x9005, 0x028f, 0x1f51, 0x1007, PQI_HWIF_SRCV, "SmartHBA P6600-8i8e"},
{0x9005, 0x028f, 0x1f51, 0x1009, PQI_HWIF_SRCV, "SmartHBA P6600-16e"},
{0x9005, 0x028f, 0x1cf2, 0x54dc, PQI_HWIF_SRCV, "ZTE SmartIOC2200 RM346-16i"},
{0x9005, 0x028f, 0x1cf2, 0x0806, PQI_HWIF_SRCV, "ZTE SmartIOC2200 RS346-16i"},
/* (MSCC PM8264 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x14b0, PQI_HWIF_SRCV, "SmartRAID 3254-16i"},
{0x9005, 0x028f, 0x9005, 0x14b1, PQI_HWIF_SRCV, "SmartRAID 3258-16i"},
{0x9005, 0x028f, 0x1f51, 0x1006, PQI_HWIF_SRCV, "SmartRAID P7608-16i"},
{0x9005, 0x028f, 0x1f51, 0x1008, PQI_HWIF_SRCV, "SmartRAID P7608-8i8e"},
{0x9005, 0x028f, 0x1f51, 0x100a, PQI_HWIF_SRCV, "SmartRAID P7608-16e"},
{0x9005, 0x028f, 0x1cf2, 0x54da, PQI_HWIF_SRCV, "ZTE SmartROC3200 RM344-16i 4G"},
{0x9005, 0x028f, 0x1cf2, 0x54db, PQI_HWIF_SRCV, "ZTE SmartROC3200 RM345-16i 8G"},
{0x9005, 0x028f, 0x1cf2, 0x0804, PQI_HWIF_SRCV, "ZTE SmartROC3200 RS344-16i 4G"},
{0x9005, 0x028f, 0x1cf2, 0x0805, PQI_HWIF_SRCV, "ZTE SmartROC3200 RS345-16i 8G"},
/* (MSCC PM8265 16x12G based) */
{0x9005, 0x028f, 0x1590, 0x02dc, PQI_HWIF_SRCV, "SR416i-a Gen10+"},
{0x9005, 0x028f, 0x9005, 0x1470, PQI_HWIF_SRCV, "SmartRAID 3200"},
{0x9005, 0x028f, 0x9005, 0x1471, PQI_HWIF_SRCV, "SmartRAID 3254-16i /e"},
{0x9005, 0x028f, 0x9005, 0x1472, PQI_HWIF_SRCV, "SmartRAID 3258-16i /e"},
{0x9005, 0x028f, 0x9005, 0x1473, PQI_HWIF_SRCV, "SmartRAID 3284-16io /e/uC"},
{0x9005, 0x028f, 0x9005, 0x1474, PQI_HWIF_SRCV, "SmartRAID 3254-16io /e"},
{0x9005, 0x028f, 0x9005, 0x1475, PQI_HWIF_SRCV, "SmartRAID 3254-16e /e"},
/* (MSCC PM8266 16x12G based) */
{0x9005, 0x028f, 0x1014, 0x0718, PQI_HWIF_SRCV, "IBM 4-Port 24G SAS"},
{0x9005, 0x028f, 0x9005, 0x1490, PQI_HWIF_SRCV, "HBA 1200p Ultra"},
{0x9005, 0x028f, 0x9005, 0x1491, PQI_HWIF_SRCV, "SmartHBA 2200p Ultra"},
{0x9005, 0x028f, 0x9005, 0x1402, PQI_HWIF_SRCV, "HBA Ultra 1200P-16i"},
{0x9005, 0x028f, 0x9005, 0x1441, PQI_HWIF_SRCV, "HBA Ultra 1200P-32i"},
/* (MSCC PM8268 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x14d0, PQI_HWIF_SRCV, "SmartRAID Ultra 3258P-16i"},
/* (MSCC PM8269 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1400, PQI_HWIF_SRCV, "SmartRAID Ultra 3258P-16i /e"},
/* (MSCC PM8270 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1410, PQI_HWIF_SRCV, "HBA Ultra 1200P-16e"},
{0x9005, 0x028f, 0x9005, 0x1411, PQI_HWIF_SRCV, "HBA 1200 Ultra"},
{0x9005, 0x028f, 0x9005, 0x1412, PQI_HWIF_SRCV, "SmartHBA 2200 Ultra"},
{0x9005, 0x028f, 0x9005, 0x1463, PQI_HWIF_SRCV, "SmartHBA 2200-8io /e"},
{0x9005, 0x028f, 0x9005, 0x14c2, PQI_HWIF_SRCV, "SmartHBA 2200-16io /e"},
/* (MSCC PM8271 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x14e0, PQI_HWIF_SRCV, "SmartIOC PM8271"},
/* (MSCC PM8272 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1420, PQI_HWIF_SRCV, "SmartRAID Ultra 3254-16e"},
/* (MSCC PM8273 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1430, PQI_HWIF_SRCV, "SmartRAID Ultra 3254-16e /e"},
/* (MSCC PM8274 16x12G based) */
{0x9005, 0x028f, 0x1e93, 0x1000, PQI_HWIF_SRCV, "ByteHBA JGH43024-8"},
{0x9005, 0x028f, 0x1e93, 0x1001, PQI_HWIF_SRCV, "ByteHBA JGH43034-8"},
{0x9005, 0x028f, 0x1e93, 0x1005, PQI_HWIF_SRCV, "ByteHBA JGH43014-8"},
/* (MSCC PM8275 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x14f0, PQI_HWIF_SRCV, "SmartIOC PM8275"},
/* (MSCC PM8276 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1480, PQI_HWIF_SRCV, "SmartRAID 3200 Ultra"},
{0x9005, 0x028f, 0x1e93, 0x1002, PQI_HWIF_SRCV, "ByteHBA JGH44014-8"},
/* (MSCC PM8278 16x12G based) */
{0x9005, 0x028f, 0x9005, 0x1440, PQI_HWIF_SRCV, "SmartRAID Ultra 3258P-32i"},
/* (MSCC PM8279 32x12G based) */
{0x9005, 0x028f, 0x9005, 0x1450, PQI_HWIF_SRCV, "SmartRAID Ultra 3258P-32i /e"},
{0x9005, 0x028f, 0x1590, 0x0294, PQI_HWIF_SRCV, "SR932i-p Gen10+"},
{0x9005, 0x028f, 0x1590, 0x0381, PQI_HWIF_SRCV, "SR932i-p Gen11"},
{0x9005, 0x028f, 0x1590, 0x0382, PQI_HWIF_SRCV, "SR308i-p Gen11"},
{0x9005, 0x028f, 0x1590, 0x0383, PQI_HWIF_SRCV, "SR308i-o Gen11"},
{0x9005, 0x028f, 0x1590, 0x02db, PQI_HWIF_SRCV, "SR416ie-m Gen11"},
{0x9005, 0x028f, 0x1590, 0x032e, PQI_HWIF_SRCV, "SR416i-o Gen11"},
{0x9005, 0x028f, 0x9005, 0x1452, PQI_HWIF_SRCV, "SmartRAID 3200p Ultra"},
/* (MSCC HBA/SMARTHBA/CFF SmartRAID - Lenovo 8X12G 16X12G based) */
{0x9005, 0x028f, 0x1d49, 0x0220, PQI_HWIF_SRCV, "4350-8i SAS/SATA HBA"},
{0x9005, 0x028f, 0x1d49, 0x0221, PQI_HWIF_SRCV, "4350-16i SAS/SATA HBA"},
{0x9005, 0x028f, 0x1d49, 0x0520, PQI_HWIF_SRCV, "5350-8i"},
{0x9005, 0x028f, 0x1d49, 0x0522, PQI_HWIF_SRCV, "5350-8i INTR"},
{0x9005, 0x028f, 0x1d49, 0x0620, PQI_HWIF_SRCV, "9350-8i 2GB Flash"},
{0x9005, 0x028f, 0x1d49, 0x0621, PQI_HWIF_SRCV, "9350-8i 2GB Flash INTR"},
{0x9005, 0x028f, 0x1d49, 0x0622, PQI_HWIF_SRCV, "9350-16i 4GB Flash"},
{0x9005, 0x028f, 0x1d49, 0x0623, PQI_HWIF_SRCV, "9350-16i 4GB Flash INTR"},
{0, 0, 0, 0, 0, 0}
};
struct pqi_ident
pqi_family_identifiers[] = {
{0x9005, 0x028f, 0, 0, PQI_HWIF_SRCV, "Smart Array Storage Controller"},
{0, 0, 0, 0, 0, 0}
};
* Logging levels global
*/
unsigned long logging_level = PQISRC_LOG_LEVEL;
/*
* Function to identify the installed adapter.
@ -404,10 +128,12 @@ static void read_device_hint_resource(struct pqisrc_softstate *softs,
{
DBG_FUNC("IN\n");
long result = 0;
device_t dev = softs->os_specific.pqi_dev;
if (resource_long_value("smartpqi", device_get_unit(dev), keyword, (long *)value) == DEVICE_HINT_SUCCESS) {
if (*value) {
if (resource_long_value("smartpqi", device_get_unit(dev), keyword, &result) == DEVICE_HINT_SUCCESS) {
if (result) {
/* set resource to 1 for disabling the
* firmware feature in device hint file. */
*value = 0;
@ -434,11 +160,14 @@ static void read_device_hint_decimal_value(struct pqisrc_softstate *softs,
{
DBG_FUNC("IN\n");
long result = 0;
device_t dev = softs->os_specific.pqi_dev;
if (resource_long_value("smartpqi", device_get_unit(dev), keyword, (long *)value) == DEVICE_HINT_SUCCESS) {
if (resource_long_value("smartpqi", device_get_unit(dev), keyword, &result) == DEVICE_HINT_SUCCESS) {
/* Nothing to do here. Value reads
* directly from Device.Hint file */
*value = result;
}
else {
/* Set to max to determine the value */
@ -482,13 +211,23 @@ static void smartpqi_read_all_device_hint_file_entries(struct pqisrc_softstate *
read_device_hint_decimal_value(softs, SCATTER_GATHER_COUNT, &value);
softs->hint.sg_segments = value;
/* hint.smartpqi.0.queue_count = "0" */
read_device_hint_decimal_value(softs, QUEUE_COUNT, &value);
softs->hint.cpu_count = value;
DBG_FUNC("IN\n");
}
/* Get the driver parameter tunables. */
static void
smartpqi_get_tunables(void)
{
/*
* Temp variable used to get the value from loader.conf.
* Initializing it with the current logging level value.
*/
unsigned long logging_level_temp = PQISRC_LOG_LEVEL;
TUNABLE_ULONG_FETCH("hw.smartpqi.debug_level", &logging_level_temp);
DBG_SET_LOGGING_LEVEL(logging_level_temp);
}
/*
* Allocate resources for our device, set up the bus interface.
@ -506,7 +245,7 @@ smartpqi_attach(device_t dev)
rcb_t *rcbp = NULL;
/*
* Initialise softc.
* Initialize softc.
*/
softs = device_get_softc(dev);
@ -518,6 +257,8 @@ smartpqi_attach(device_t dev)
memset(softs, 0, sizeof(*softs));
softs->os_specific.pqi_dev = dev;
smartpqi_get_tunables();
DBG_FUNC("IN\n");
/* assume failure is 'not configured' */
@ -830,4 +571,5 @@ static driver_t smartpqi_pci_driver = {
};
DRIVER_MODULE(smartpqi, pci, smartpqi_pci_driver, 0, 0);
MODULE_DEPEND(smartpqi, pci, 1, 1, 1);

28
sys/dev/smartpqi/smartpqi_misc.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -58,7 +58,7 @@ void
os_wellness_periodic(void *data)
{
struct pqisrc_softstate *softs = (struct pqisrc_softstate *)data;
int ret = 0;
int ret;
/* update time to FW */
if (!pqisrc_ctrl_offline(softs)){
@ -286,27 +286,3 @@ bsd_set_hint_adapter_cap(struct pqisrc_softstate *softs)
DBG_FUNC("OUT\n");
}
void
bsd_set_hint_adapter_cpu_config(struct pqisrc_softstate *softs)
{
DBG_FUNC("IN\n");
/* online cpu count decides the no.of queues the driver can create,
* and msi interrupt count as well.
* If the cpu count is "zero" set by hint file then the driver
* can have "one" queue and "one" legacy interrupt. (It shares event queue for
* operational IB queue).
* Check for os_get_intr_config function for interrupt assignment.*/
if (softs->hint.cpu_count > softs->num_cpus_online) {
/* Nothing to do here. Supported cpu count
* already fetched from hardware */
}
else {
/* Set Device.Hint cpu count here */
softs->num_cpus_online = softs->hint.cpu_count;
}
DBG_FUNC("OUT\n");
}

52
sys/dev/smartpqi/smartpqi_prototypes.h
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -84,23 +84,23 @@ uint32_t pqisrc_get_tag(lockless_stack_t *);
/* smartpqi_discovery.c */
void pqisrc_remove_device(pqisrc_softstate_t *, pqi_scsi_dev_t *);
boolean_t pqisrc_add_softs_entry(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device,
uint8_t *scsi3addr);
uint8_t const *scsi3addr);
int pqisrc_get_ctrl_fw_version(pqisrc_softstate_t *);
int pqisrc_rescan_devices(pqisrc_softstate_t *);
int pqisrc_scan_devices(pqisrc_softstate_t *);
void pqisrc_cleanup_devices(pqisrc_softstate_t *);
void pqisrc_device_mem_free(pqisrc_softstate_t *, pqi_scsi_dev_t *);
boolean_t pqisrc_is_external_raid_device(pqi_scsi_dev_t *device);
boolean_t pqisrc_is_external_raid_device(pqi_scsi_dev_t const *device);
void pqisrc_free_device(pqisrc_softstate_t * softs,pqi_scsi_dev_t *device);
void pqisrc_init_bitmap(pqisrc_softstate_t *softs);
void pqisrc_remove_target_bit(pqisrc_softstate_t *softs, int target);
int pqisrc_find_avail_target(pqisrc_softstate_t *softs);
int pqisrc_find_device_list_index(pqisrc_softstate_t *softs,
pqi_scsi_dev_t *device);
pqi_scsi_dev_t const *device);
int pqisrc_find_btl_list_index(pqisrc_softstate_t *softs,
int bus, int target, int lun);
int pqisrc_delete_softs_entry(pqisrc_softstate_t *softs,
pqi_scsi_dev_t *device);
pqi_scsi_dev_t const *device);
int pqisrc_get_physical_logical_luns(pqisrc_softstate_t *softs, uint8_t cmd,
reportlun_data_ext_t **buff, size_t *data_length);
int pqisrc_send_scsi_inquiry(pqisrc_softstate_t *softs,
@ -112,16 +112,16 @@ int pqisrc_prepare_send_raid(pqisrc_softstate_t *, pqisrc_raid_req_t *,
/* smartpqi_helper.c */
boolean_t pqisrc_ctrl_offline(pqisrc_softstate_t *);
boolean_t pqisrc_ctrl_offline(pqisrc_softstate_t const *);
void pqisrc_heartbeat_timer_handler(pqisrc_softstate_t *);
int pqisrc_wait_on_condition(pqisrc_softstate_t *softs, rcb_t *rcb,
uint32_t timeout);
boolean_t pqisrc_device_equal(pqi_scsi_dev_t *, pqi_scsi_dev_t *);
boolean_t pqisrc_is_hba_lunid(uint8_t *);
boolean_t pqisrc_is_logical_device(pqi_scsi_dev_t *);
boolean_t pqisrc_device_equal(pqi_scsi_dev_t const *, pqi_scsi_dev_t const *);
boolean_t pqisrc_is_hba_lunid(uint8_t const*);
boolean_t pqisrc_is_logical_device(pqi_scsi_dev_t const *);
void pqisrc_sanitize_inquiry_string(unsigned char *, int );
void pqisrc_display_device_info(pqisrc_softstate_t *, char *, pqi_scsi_dev_t *);
boolean_t pqisrc_scsi3addr_equal(uint8_t *, uint8_t *);
void pqisrc_display_device_info(pqisrc_softstate_t *, char const *, pqi_scsi_dev_t *);
boolean_t pqisrc_scsi3addr_equal(uint8_t const *, uint8_t const *);
void check_struct_sizes(void);
char *pqisrc_raidlevel_to_string(uint8_t);
void pqisrc_configure_legacy_intx(pqisrc_softstate_t*, boolean_t);
@ -151,7 +151,7 @@ void pqisrc_show_aio_error_info(pqisrc_softstate_t *softs, rcb_t *rcb,
aio_path_error_info_elem_t *aio_err);
void pqisrc_show_raid_error_info(pqisrc_softstate_t *softs, rcb_t *rcb,
raid_path_error_info_elem_t *aio_err);
boolean_t suppress_innocuous_error_prints(pqisrc_softstate_t *softs,
boolean_t suppress_innocuous_error_prints(pqisrc_softstate_t const *softs,
rcb_t *rcb);
uint8_t pqisrc_get_cmd_from_rcb(rcb_t *);
boolean_t pqisrc_is_innocuous_error(pqisrc_softstate_t *, rcb_t *, void *);
@ -163,37 +163,40 @@ int pqisrc_build_send_vendor_request(pqisrc_softstate_t *softs,
int pqisrc_build_send_io(pqisrc_softstate_t *,rcb_t *);
int pqisrc_build_scsi_cmd_raidbypass(pqisrc_softstate_t *softs,
pqi_scsi_dev_t *device, rcb_t *rcb);
int pqisrc_send_tmf(pqisrc_softstate_t *, pqi_scsi_dev_t *,
int pqisrc_send_tmf(pqisrc_softstate_t *, pqi_scsi_dev_t const *,
rcb_t *, rcb_t *, int);
int pqisrc_write_current_time_to_host_wellness(pqisrc_softstate_t *softs);
int pqisrc_write_driver_version_to_host_wellness(pqisrc_softstate_t *softs);
extern inline void pqisrc_aio_build_cdb(aio_req_locator_t *, uint32_t,
rcb_t *, uint8_t *);
extern inline boolean_t pqisrc_aio_req_too_big(pqisrc_softstate_t *, pqi_scsi_dev_t *,
rcb_t const *, aio_req_locator_t *, uint32_t);
void pqisrc_build_aio_common(pqisrc_softstate_t *, pqi_aio_req_t *,
rcb_t *, uint32_t);
void pqisrc_build_aio_R1_write(pqisrc_softstate_t *,
pqi_aio_raid1_write_req_t *, rcb_t *, uint32_t);
void pqisrc_build_aio_R5or6_write(pqisrc_softstate_t *,
pqi_aio_raid5or6_write_req_t *, rcb_t *, uint32_t);
void pqisrc_show_cdb(pqisrc_softstate_t *softs, char *msg, rcb_t *rcb, uint8_t *cdb);
void pqisrc_print_buffer(pqisrc_softstate_t *softs, char *msg, void *user_buf, uint32_t total_len, uint32_t flags);
void pqisrc_show_cdb(pqisrc_softstate_t *softs, char const *msg, rcb_t const *rcb, uint8_t *cdb);
void pqisrc_print_buffer(pqisrc_softstate_t *softs, char const *msg, void *user_buf, uint32_t total_len, uint32_t flags);
void pqisrc_show_rcb_details(pqisrc_softstate_t *softs, rcb_t *rcb, char *msg, void *err_info);
void pqisrc_show_aio_io(pqisrc_softstate_t *, rcb_t *,
pqi_aio_req_t *, uint32_t);
void pqisrc_show_aio_common(pqisrc_softstate_t *, rcb_t *, pqi_aio_req_t *);
void pqisrc_show_aio_R1_write(pqisrc_softstate_t *, rcb_t *,
void pqisrc_show_aio_common(pqisrc_softstate_t *, rcb_t const *, pqi_aio_req_t *);
void pqisrc_show_aio_R1_write(pqisrc_softstate_t *, rcb_t const *,
pqi_aio_raid1_write_req_t *);
void pqisrc_show_aio_R5or6_write(pqisrc_softstate_t *, rcb_t *,
void pqisrc_show_aio_R5or6_write(pqisrc_softstate_t *, rcb_t const *,
pqi_aio_raid5or6_write_req_t *);
boolean_t pqisrc_cdb_is_write(uint8_t *);
void print_this_counter(pqisrc_softstate_t *softs, io_counters_t *pcounter, char *msg);
boolean_t pqisrc_cdb_is_write(uint8_t const *);
void print_this_counter(pqisrc_softstate_t const *softs, io_counters_t const *pcounter, char const *msg);
void print_all_counters(pqisrc_softstate_t *softs, uint32_t flags);
char *io_path_to_ascii(IO_PATH_T path);
void int_to_scsilun(uint64_t, uint8_t *);
boolean_t pqisrc_cdb_is_read(uint8_t *);
boolean_t pqisrc_cdb_is_read(uint8_t const *);
void pqisrc_build_aio_io(pqisrc_softstate_t *, rcb_t *, pqi_aio_req_t *, uint32_t);
uint8_t pqisrc_get_aio_data_direction(rcb_t *);
uint8_t pqisrc_get_raid_data_direction(rcb_t *);
void dump_tmf_details(pqisrc_softstate_t *, rcb_t *, char *);
io_type_t get_io_type_from_cdb(uint8_t *);
io_type_t get_io_type_from_cdb(uint8_t const *);
OS_ATOMIC64_T increment_this_counter(io_counters_t *, IO_PATH_T , io_type_t );
boolean_t
is_buffer_zero(void *, uint32_t );
@ -237,7 +240,7 @@ int pqisrc_delete_op_queue(pqisrc_softstate_t *, uint32_t, boolean_t);
void pqisrc_destroy_event_queue(pqisrc_softstate_t *);
void pqisrc_destroy_op_ib_queues(pqisrc_softstate_t *);
void pqisrc_destroy_op_ob_queues(pqisrc_softstate_t *);
int pqisrc_change_op_ibq_queue_prop(pqisrc_softstate_t *, ib_queue_t *,
int pqisrc_change_op_ibq_queue_prop(pqisrc_softstate_t *, ib_queue_t const *,
uint32_t);
int pqisrc_create_op_obq(pqisrc_softstate_t *, ob_queue_t *);
int pqisrc_create_op_ibq(pqisrc_softstate_t *, ib_queue_t *);
@ -287,7 +290,6 @@ int os_destroy_semaphore(struct sema *);
void os_sema_lock(struct sema *);
void os_sema_unlock(struct sema *);
void bsd_set_hint_adapter_cap(struct pqisrc_softstate *);
void bsd_set_hint_adapter_cpu_config(struct pqisrc_softstate *);
int os_strlcpy(char *dst, char *src, int len);
void os_complete_outstanding_cmds_nodevice(pqisrc_softstate_t *);

25
sys/dev/smartpqi/smartpqi_queue.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -514,11 +514,7 @@ pqisrc_destroy_event_queue(pqisrc_softstate_t *softs)
DBG_FUNC("IN\n");
if (softs->event_q.created == true) {
int ret = PQI_STATUS_SUCCESS;
ret = pqisrc_delete_op_queue(softs, softs->event_q.q_id, false);
if (ret) {
DBG_ERR("Failed to Delete Event Q %u\n", softs->event_q.q_id);
}
pqisrc_delete_op_queue(softs, softs->event_q.q_id, false);
softs->event_q.created = false;
}
@ -535,7 +531,7 @@ pqisrc_destroy_event_queue(pqisrc_softstate_t *softs)
void
pqisrc_destroy_op_ib_queues(pqisrc_softstate_t *softs)
{
int ret = PQI_STATUS_SUCCESS;
ib_queue_t *op_ib_q = NULL;
uint32_t total_op_ibq = softs->num_op_raid_ibq;
int i;
@ -548,12 +544,7 @@ pqisrc_destroy_op_ib_queues(pqisrc_softstate_t *softs)
op_ib_q = &softs->op_raid_ib_q[i];
release_queue:
if (op_ib_q->created == true) {
ret = pqisrc_delete_op_queue(softs, op_ib_q->q_id,
true);
if (ret) {
DBG_ERR("Failed to Delete IB Q %u\n",
op_ib_q->q_id);
}
pqisrc_delete_op_queue(softs, op_ib_q->q_id, true);
op_ib_q->created = false;
}
@ -582,7 +573,6 @@ release_queue:
void
pqisrc_destroy_op_ob_queues(pqisrc_softstate_t *softs)
{
int ret = PQI_STATUS_SUCCESS;
int i;
ob_queue_t *op_ob_q = NULL;
@ -592,10 +582,7 @@ pqisrc_destroy_op_ob_queues(pqisrc_softstate_t *softs)
op_ob_q = &softs->op_ob_q[i];
if (op_ob_q->created == true) {
ret = pqisrc_delete_op_queue(softs, op_ob_q->q_id, false);
if (ret) {
DBG_ERR("Failed to Delete OB Q %u\n",op_ob_q->q_id);
}
pqisrc_delete_op_queue(softs, op_ob_q->q_id, false);
op_ob_q->created = false;
}
@ -643,7 +630,7 @@ pqisrc_destroy_admin_queue(pqisrc_softstate_t *softs)
*/
int
pqisrc_change_op_ibq_queue_prop(pqisrc_softstate_t *softs,
ib_queue_t *op_ib_q, uint32_t prop)
ib_queue_t const *op_ib_q, uint32_t prop)
{
int ret = PQI_STATUS_SUCCESS;
gen_adm_req_iu_t admin_req;

104
sys/dev/smartpqi/smartpqi_request.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -85,8 +85,8 @@ pqisrc_contiguous_free_elem(uint32_t pi, uint32_t ci, uint32_t elem_in_q)
/* Subroutine to find out num of elements need for the request */
static uint32_t
pqisrc_num_elem_needed(pqisrc_softstate_t *softs, uint32_t SG_Count,
pqi_scsi_dev_t *devp, boolean_t is_write, IO_PATH_T io_path)
pqisrc_num_elem_needed(pqisrc_softstate_t const *softs, uint32_t SG_Count,
pqi_scsi_dev_t const *devp, boolean_t is_write, IO_PATH_T io_path)
{
uint32_t num_sg;
uint32_t num_elem_required = 1;
@ -129,7 +129,7 @@ pqisrc_build_sgl(sgt_t *sg_array, rcb_t *rcb, iu_header_t *iu_hdr,
DBG_FUNC("IN\n");
/* DBG_IO("SGL_Count :%d",num_sg); */
/* DBG_IO("SGL_Count :%d\n",num_sg); */
if (0 == num_sg) {
goto out;
}
@ -404,11 +404,11 @@ pqisrc_build_aio_common(pqisrc_softstate_t *softs, pqi_aio_req_t *aio_req,
}
/*Subroutine used to show standard AIO IU fields */
void
pqisrc_show_aio_common(pqisrc_softstate_t *softs, rcb_t *rcb,
pqisrc_show_aio_common(pqisrc_softstate_t *softs, rcb_t const *rcb,
pqi_aio_req_t *aio_req)
{
#ifdef DEBUG_AIO
DBG_INFO("AIO IU Content, tag# 0x%08x", rcb->tag);
DBG_INFO("AIO IU Content, tag# 0x%08x\n", rcb->tag);
DBG_INFO("%15s: 0x%x\n", "iu_type", aio_req->header.iu_type);
DBG_INFO("%15s: 0x%x\n", "comp_feat", aio_req->header.comp_feature);
DBG_INFO("%15s: 0x%x\n", "length", aio_req->header.iu_length);
@ -453,11 +453,11 @@ pqisrc_build_aio_R1_write(pqisrc_softstate_t *softs,
{
DBG_FUNC("IN\n");
if (!rcb->dvp) {
DBG_WARN("%s: DEBUG: dev ptr is null", __func__);
DBG_WARN("%s: DEBUG: dev ptr is NULL\n", __func__);
return;
}
if (!rcb->dvp->raid_map) {
DBG_WARN("%s: DEBUG: raid_map is null", __func__);
DBG_WARN("%s: DEBUG: raid_map is NULL\n", __func__);
return;
}
@ -522,12 +522,12 @@ pqisrc_build_aio_R1_write(pqisrc_softstate_t *softs,
/*Subroutine used to show AIO RAID1 Write bypass IU fields */
void
pqisrc_show_aio_R1_write(pqisrc_softstate_t *softs, rcb_t *rcb,
pqisrc_show_aio_R1_write(pqisrc_softstate_t *softs, rcb_t const *rcb,
pqi_aio_raid1_write_req_t *aio_req)
{
#ifdef DEBUG_AIO
DBG_INFO("AIO RAID1 Write IU Content, tag# 0x%08x", rcb->tag);
DBG_INFO("AIO RAID1 Write IU Content, tag# 0x%08x\n", rcb->tag);
DBG_INFO("%15s: 0x%x\n", "iu_type", aio_req->header.iu_type);
DBG_INFO("%15s: 0x%x\n", "comp_feat", aio_req->header.comp_feature);
DBG_INFO("%15s: 0x%x\n", "length", aio_req->header.iu_length);
@ -674,7 +674,7 @@ pqisrc_build_aio_R5or6_write(pqisrc_softstate_t *softs,
/*Subroutine used to show AIO RAID5/6 Write bypass IU fields */
void
pqisrc_show_aio_R5or6_write(pqisrc_softstate_t *softs, rcb_t *rcb,
pqisrc_show_aio_R5or6_write(pqisrc_softstate_t *softs, rcb_t const *rcb,
pqi_aio_raid5or6_write_req_t *aio_req)
{
#ifdef DEBUG_AIO
@ -724,7 +724,7 @@ pqisrc_show_aio_R5or6_write(pqisrc_softstate_t *softs, rcb_t *rcb,
/* Is the cdb a read command? */
boolean_t
pqisrc_cdb_is_read(uint8_t *cdb)
pqisrc_cdb_is_read(uint8_t const *cdb)
{
if (cdb[0] == SCMD_READ_6 || cdb[0] == SCMD_READ_10 ||
cdb[0] == SCMD_READ_12 || cdb[0] == SCMD_READ_16)
@ -734,7 +734,7 @@ pqisrc_cdb_is_read(uint8_t *cdb)
/* Is the cdb a write command? */
boolean_t
pqisrc_cdb_is_write(uint8_t *cdb)
pqisrc_cdb_is_write(uint8_t const *cdb)
{
if (cdb == NULL)
return false;
@ -1021,7 +1021,7 @@ pqisrc_build_send_io(pqisrc_softstate_t *softs,rcb_t *rcb)
/* coverity[unchecked_value] */
num_elem_needed = pqisrc_num_elem_needed(softs,
OS_GET_IO_SG_COUNT(rcb), devp, is_write, io_path);
DBG_IO("num_elem_needed :%u",num_elem_needed);
DBG_IO("num_elem_needed :%u\n",num_elem_needed);
do {
uint32_t num_elem_available;
@ -1047,7 +1047,7 @@ pqisrc_build_send_io(pqisrc_softstate_t *softs,rcb_t *rcb)
}
}while(TraverseCount < 2);
DBG_IO("num_elem_alloted :%u",num_elem_alloted);
DBG_IO("num_elem_alloted :%u\n",num_elem_alloted);
if (num_elem_alloted == 0) {
DBG_WARN("OUT: IB Queues were full\n");
return PQI_STATUS_QFULL;
@ -1131,7 +1131,7 @@ fill_lba_for_scsi_rw(pqisrc_softstate_t *softs, uint8_t *cdb, aio_req_locator_t
{
if (!l) {
DBG_INFO("No locator ptr: AIO ineligible");
DBG_INFO("No locator ptr: AIO ineligible\n");
return PQI_STATUS_FAILURE;
}
@ -1172,7 +1172,7 @@ fill_lba_for_scsi_rw(pqisrc_softstate_t *softs, uint8_t *cdb, aio_req_locator_t
break;
default:
/* Process via normal I/O path. */
DBG_AIO("NOT read or write 6/10/12/16: AIO ineligible");
DBG_AIO("NOT read or write 6/10/12/16: AIO ineligible\n");
return PQI_STATUS_FAILURE;
}
return PQI_STATUS_SUCCESS;
@ -1180,9 +1180,9 @@ fill_lba_for_scsi_rw(pqisrc_softstate_t *softs, uint8_t *cdb, aio_req_locator_t
/* determine whether writes to certain types of RAID are supported. */
static boolean_t
pqisrc_is_supported_write(pqisrc_softstate_t *softs,
pqi_scsi_dev_t *device)
inline boolean_t
pqisrc_is_supported_write(pqisrc_softstate_t const *softs,
pqi_scsi_dev_t const *device)
{
DBG_FUNC("IN\n");
@ -1381,7 +1381,7 @@ pqisrc_is_r5or6_single_group(pqisrc_softstate_t *softs, aio_req_locator_t *l)
l->r5or6.row.blks_per_row;
if (l->group.first != l->group.last) {
DBG_AIO("AIO ineligible");
DBG_AIO("AIO ineligible\n");
ret = false;
}
@ -1403,7 +1403,7 @@ pqisrc_is_r5or6_single_row(pqisrc_softstate_t *softs, aio_req_locator_t *l)
l->r5or6.row.last = l->block.last / l->stripesz;
if (l->r5or6.row.first != l->r5or6.row.last) {
DBG_AIO("AIO ineligible");
DBG_AIO("AIO ineligible\n");
ret = false;
}
@ -1431,7 +1431,7 @@ pqisrc_is_r5or6_single_column(pqisrc_softstate_t *softs, aio_req_locator_t *l)
l->r5or6.col.last = l->r5or6.row.offset_last / l->strip_sz;
if (l->r5or6.col.first != l->r5or6.col.last) {
DBG_AIO("AIO ineligible");
DBG_AIO("AIO ineligible\n");
ret = false;
}
@ -1492,9 +1492,9 @@ pqisrc_handle_blk_size_diffs(aio_req_locator_t *l)
* handle based on dev type, Raid level, and encryption status.
* TODO: make limits dynamic when this becomes possible.
*/
static boolean_t
inline boolean_t
pqisrc_aio_req_too_big(pqisrc_softstate_t *softs,
pqi_scsi_dev_t *device, rcb_t *rcb,
pqi_scsi_dev_t *device, rcb_t const *rcb,
aio_req_locator_t *l, uint32_t disk_blk_cnt)
{
boolean_t ret = false;
@ -1537,7 +1537,7 @@ pqisrc_aio_req_too_big(pqisrc_softstate_t *softs,
if (size > dev_max) {
DBG_AIO("AIO ineligible: size=%u, max=%u", size, dev_max);
DBG_AIO("AIO ineligible: size=%u, max=%u\n", size, dev_max);
ret = true;
}
@ -1547,7 +1547,7 @@ pqisrc_aio_req_too_big(pqisrc_softstate_t *softs,
#ifdef DEBUG_RAID_MAP
static inline void
pqisrc_aio_show_raid_map(pqisrc_softstate_t *softs, struct raid_map *m)
pqisrc_aio_show_raid_map(pqisrc_softstate_t const *softs, struct raid_map const *m)
{
int i;
@ -1583,7 +1583,7 @@ pqisrc_aio_show_raid_map(pqisrc_softstate_t *softs, struct raid_map *m)
static inline void
pqisrc_aio_show_locator_info(pqisrc_softstate_t *softs,
aio_req_locator_t *l, uint32_t disk_blk_cnt, rcb_t *rcb)
aio_req_locator_t *l, uint32_t disk_blk_cnt, rcb_t const *rcb)
{
#ifdef DEBUG_AIO_LOCATOR
pqisrc_aio_show_raid_map(softs, l->raid_map);
@ -1636,7 +1636,7 @@ pqisrc_aio_show_locator_info(pqisrc_softstate_t *softs,
}
/* build the aio cdb */
static void
inline void
pqisrc_aio_build_cdb(aio_req_locator_t *l,
uint32_t disk_blk_cnt, rcb_t *rcb, uint8_t *cdb)
{
@ -1665,7 +1665,7 @@ pqisrc_aio_build_cdb(aio_req_locator_t *l,
/* print any arbitrary buffer of length total_len */
void
pqisrc_print_buffer(pqisrc_softstate_t *softs, char *msg, void *user_buf,
pqisrc_print_buffer(pqisrc_softstate_t *softs, char const *msg, void *user_buf,
uint32_t total_len, uint32_t flags)
{
#define LINE_BUF_LEN 60
@ -1713,7 +1713,7 @@ pqisrc_print_buffer(pqisrc_softstate_t *softs, char *msg, void *user_buf,
/* print CDB with column header */
void
pqisrc_show_cdb(pqisrc_softstate_t *softs, char *msg, rcb_t *rcb, uint8_t *cdb)
pqisrc_show_cdb(pqisrc_softstate_t *softs, char const *msg, rcb_t const *rcb, uint8_t *cdb)
{
/* Print the CDB contents */
pqisrc_print_buffer(softs, msg, cdb, rcb->cmdlen, PRINT_FLAG_HDR_COLUMN);
@ -1742,7 +1742,7 @@ pqisrc_show_rcb_details(pqisrc_softstate_t *softs, rcb_t *rcb, char *msg, void *
DBG_INFO("tag=0x%x dir=%u host_timeout=%ums\n", rcb->tag,
rcb->data_dir, (uint32_t)rcb->host_timeout_ms);
DBG_INFO("BTL: %d:%d:%d addr=0x%x\n", devp->bus, devp->target,
DBG_INFO("B%d:T%d:L%d addr=0x%x\n", devp->bus, devp->target,
devp->lun, GET_LE32(devp->scsi3addr));
if (rcb->path == AIO_PATH)
@ -1786,7 +1786,7 @@ pqisrc_build_scsi_cmd_raidbypass(pqisrc_softstate_t *softs,
return PQI_STATUS_FAILURE;
}
if (device->raid_map == NULL) {
DBG_INFO("tag=0x%x BTL: %d:%d:%d Raid map is NULL\n",
DBG_INFO("tag=0x%x B%d:T%d:L%d Raid map is NULL\n",
rcb->tag, device->bus, device->target, device->lun);
return PQI_STATUS_FAILURE;
}
@ -1846,15 +1846,18 @@ pqisrc_build_scsi_cmd_raidbypass(pqisrc_softstate_t *softs,
}
if (l->map.idx >= RAID_MAP_MAX_ENTRIES) {
DBG_INFO("AIO ineligible: index exceeds max map entries");
DBG_INFO("AIO ineligible: index exceeds max map entries\n");
return PQI_STATUS_FAILURE;
}
rcb->ioaccel_handle =
l->raid_map->dev_data[l->map.idx].ioaccel_handle;
/*
if (!pqisrc_calc_aio_block(l))
return PQI_STATUS_FAILURE;
*/
pqisrc_calc_aio_block(l);
disk_blk_cnt = pqisrc_handle_blk_size_diffs(l);
@ -1889,8 +1892,8 @@ pqisrc_build_scsi_cmd_raidbypass(pqisrc_softstate_t *softs,
*/
static int
pqisrc_send_aio_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t *devp,
rcb_t *rcb, rcb_t *rcb_to_manage, int tmf_type)
pqisrc_send_aio_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t const *devp,
rcb_t *rcb, rcb_t const *rcb_to_manage, int tmf_type)
{
int rval = PQI_STATUS_SUCCESS;
pqi_aio_tmf_req_t tmf_req;
@ -1966,8 +1969,8 @@ pqisrc_send_aio_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t *devp,
/* Function used to submit a Raid TMF to the adapter */
static int
pqisrc_send_raid_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t *devp,
rcb_t *rcb, rcb_t *rcb_to_manage, int tmf_type)
pqisrc_send_raid_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t const *devp,
rcb_t *rcb, rcb_t const *rcb_to_manage, int tmf_type)
{
int rval = PQI_STATUS_SUCCESS;
pqi_raid_tmf_req_t tmf_req;
@ -1997,9 +2000,6 @@ pqisrc_send_raid_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t *devp,
tmf_type == SOP_TASK_MANAGEMENT_LUN_RESET) {
/* OS_TMF_TIMEOUT_SEC - 1 to accomodate driver processing */
tmf_req.timeout_in_sec = OS_TMF_TIMEOUT_SEC - 1;
/* if OS tmf timeout is 0, set minimum value for timeout */
if (!tmf_req.timeout_in_sec)
tmf_req.timeout_in_sec = 1;
}
op_ib_q = &softs->op_raid_ib_q[0];
@ -2034,8 +2034,8 @@ pqisrc_send_raid_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t *devp,
return rval;
}
void
dump_tmf_details(pqisrc_softstate_t *softs, rcb_t *rcb, char *msg)
static void
dump_tmf_details(rcb_t *rcb, char const *msg)
{
uint32_t qid = rcb->req_q ? rcb->req_q->q_id : -1;
@ -2045,7 +2045,7 @@ dump_tmf_details(pqisrc_softstate_t *softs, rcb_t *rcb, char *msg)
}
int
pqisrc_send_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t *devp,
pqisrc_send_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t const *devp,
rcb_t *rcb, rcb_t *rcb_to_manage, int tmf_type)
{
int ret = PQI_STATUS_SUCCESS;
@ -2062,11 +2062,11 @@ pqisrc_send_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t *devp,
if (tmf_type == SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK)
{
rcb_to_manage->host_wants_to_abort_this = true;
dump_tmf_details(softs, rcb_to_manage, "rcb_to_manage");
dump_tmf_details(rcb_to_manage, "rcb_to_manage");
}
dump_tmf_details(softs, rcb, "rcb");
dump_tmf_details(rcb, "rcb");
if(!devp->is_physical_device) {
if (tmf_type == SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK) {
@ -2167,7 +2167,7 @@ io_type_to_ascii(io_type_t io_type)
/* return the io type based on cdb */
io_type_t
get_io_type_from_cdb(uint8_t *cdb)
get_io_type_from_cdb(uint8_t const *cdb)
{
if (cdb == NULL)
return UNKNOWN_IO_TYPE;
@ -2223,9 +2223,9 @@ pqisrc_increment_io_counters(pqisrc_softstate_t *softs, rcb_t *rcb)
#if 1 /* leave this enabled while we gain confidence for each io path */
if (ret_val == 1)
{
char *raid_type = counter_type_to_raid_ascii(type_index);
char *path = io_path_to_ascii(rcb->path);
char *io_ascii = io_type_to_ascii(io_type);
char const *raid_type = counter_type_to_raid_ascii(type_index);
char const *path = io_path_to_ascii(rcb->path);
char const *io_ascii = io_type_to_ascii(io_type);
DBG_INFO("Got first path/type hit. "
"Path=%s RaidType=%s IoType=%s\n",
@ -2238,7 +2238,7 @@ pqisrc_increment_io_counters(pqisrc_softstate_t *softs, rcb_t *rcb)
/* public routine to print a particular counter with header msg */
void
print_this_counter(pqisrc_softstate_t *softs, io_counters_t *pcounter, char *msg)
print_this_counter(pqisrc_softstate_t const *softs, io_counters_t const *pcounter, char const *msg)
{
io_counters_t counter;
uint32_t percent_reads;
@ -2280,7 +2280,7 @@ print_this_counter(pqisrc_softstate_t *softs, io_counters_t *pcounter, char *msg
boolean_t
is_buffer_zero(void *buffer, uint32_t size)
{
char *buf = buffer;
char const *buf = buffer;
DWORD ii;
if (buffer == NULL || size == 0)

14
sys/dev/smartpqi/smartpqi_response.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -121,7 +121,7 @@ pqisrc_extract_sense_data(sense_data_u_t *sense_data, uint8_t *key, uint8_t *asc
if (sense_data->fixed_format.response_code == SCSI_SENSE_RESPONSE_70 ||
sense_data->fixed_format.response_code == SCSI_SENSE_RESPONSE_71)
{
sense_data_fixed_t *fixed = &sense_data->fixed_format;
sense_data_fixed_t const *fixed = &sense_data->fixed_format;
*key = fixed->sense_key;
*asc = fixed->sense_code;
@ -130,7 +130,7 @@ pqisrc_extract_sense_data(sense_data_u_t *sense_data, uint8_t *key, uint8_t *asc
else if (sense_data->descriptor_format.response_code == SCSI_SENSE_RESPONSE_72 ||
sense_data->descriptor_format.response_code == SCSI_SENSE_RESPONSE_73)
{
sense_data_descriptor_t *desc = &sense_data->descriptor_format;
sense_data_descriptor_t const *desc = &sense_data->descriptor_format;
*key = desc->sense_key;
*asc = desc->sense_code;
@ -146,7 +146,7 @@ pqisrc_extract_sense_data(sense_data_u_t *sense_data, uint8_t *key, uint8_t *asc
/* Suppress common errors unless verbose debug flag is on */
boolean_t
suppress_innocuous_error_prints(pqisrc_softstate_t *softs, rcb_t *rcb)
suppress_innocuous_error_prints(pqisrc_softstate_t const *softs, rcb_t *rcb)
{
uint8_t opcode = rcb->cdbp ? rcb->cdbp[0] : 0xFF;
@ -165,7 +165,7 @@ static void
pqisrc_show_sense_data_simple(pqisrc_softstate_t *softs, rcb_t *rcb, sense_data_u_t *sense_data)
{
uint8_t opcode = rcb->cdbp ? rcb->cdbp[0] : 0xFF;
char *path = io_path_to_ascii(rcb->path);
char const *path = io_path_to_ascii(rcb->path);
uint8_t key, asc, ascq;
pqisrc_extract_sense_data(sense_data, &key, &asc, &ascq);
@ -393,7 +393,7 @@ pqisrc_process_task_management_response(pqisrc_softstate_t *softs,
}
static int
pqisrc_process_vendor_general_response(pqi_vendor_general_response_t *response)
pqisrc_process_vendor_general_response(pqi_vendor_general_response_t const *response)
{
int ret = PQI_STATUS_SUCCESS;
@ -448,7 +448,7 @@ pqisrc_process_response_queue(pqisrc_softstate_t *softs, int oq_id)
rcb = &softs->rcb[tag];
/* Make sure we are processing a valid response. */
if ((rcb->tag != tag) || (rcb->req_pending == false)) {
DBG_ERR("No such request pending with tag : %x rcb->tag : %x", tag, rcb->tag);
DBG_ERR("No such request pending with tag : %x rcb->tag : %x\n", tag, rcb->tag);
oq_ci = (oq_ci + 1) % ob_q->num_elem;
break;
}

6
sys/dev/smartpqi/smartpqi_sis.c
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -84,7 +84,7 @@ sis_disable_intx(pqisrc_softstate_t *softs)
void
sis_disable_interrupt(pqisrc_softstate_t *softs)
{
DBG_FUNC("IN");
DBG_FUNC("IN\n");
switch(softs->intr_type) {
case INTR_TYPE_FIXED:
@ -100,7 +100,7 @@ sis_disable_interrupt(pqisrc_softstate_t *softs)
break;
}
DBG_FUNC("OUT");
DBG_FUNC("OUT\n");
}

5
sys/dev/smartpqi/smartpqi_structures.h
View file

@ -1,5 +1,5 @@
/*-
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -35,6 +35,7 @@ struct bmic_host_wellness_driver_version {
uint8_t driver_version_tag[2];
uint16_t driver_version_length;
char driver_version[32];
uint8_t dont_write_tag[2];
uint8_t end_tag[2];
}OS_ATTRIBUTE_PACKED;
@ -901,6 +902,8 @@ typedef struct pqi_scsi_device {
int *offload_to_mirror; /* Send next I/O accelerator RAID
offload request to mirror drive. */
struct raid_map *raid_map; /* I/O accelerator RAID map */
int *temp_offload_to_mirror; /* Temporary stored offload_to_mirror which will be freed later */
struct raid_map *temp_raid_map; /* Temporary stored RAID map which will be freed later */
int reset_in_progress;
int logical_unit_number;