mirror of
https://git.freebsd.org/src.git
synced 2026-01-11 19:57:22 +00:00
cae9ae66ad
There are delay loops, checking the BUSY status bit, before writing to the date or time registers. Each iteration contains a 1usec delay, for a maximum of 70 iterations. This is frequently not enough on the D1 platform, where the message is emitted: rtc0: could not set date, RTC busy Bump the loop delay to 10usecs each, and the maximum number of iterations to 150, for a maximum delay of 1.5msecs between each write of the register. In my testing this seems to be adequate. The loop variable is renamed for clarity/simplicity. Reviewed by: manu MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D54180 |
||
|---|---|---|
| .. | ||
| allwinner | ||
| annapurna/alpine | ||
| arm | ||
| broadcom/bcm2835 | ||
| conf | ||
| freescale | ||
| include | ||
| mv | ||
| nvidia | ||
| qemu | ||
| qualcomm | ||
| rockchip | ||
| ti | ||
| xilinx | ||